Commit 42803a4b authored by Dave Newbold's avatar Dave Newbold

Addr tab update

parent 78d7d4e1
-- Address decode logic for ipbus fabric
--
-- This file has been AUTOGENERATED from the address table - do not hand edit
--
-- We assume the synthesis tool is clever enough to recognise exclusive conditions
-- in the if statement.
--
-- Dave Newbold, February 2011
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package ipbus_decode_top is
constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_top(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Wed Jul 12 14:14:22 2017
constant N_SLV_CSR: integer := 0;
constant N_SLV_I2C: integer := 1;
constant N_SLV_FREQ_CTR: integer := 2;
constant N_SLAVES: integer := 3;
-- END automatically generated VHDL
end ipbus_decode_top;
package body ipbus_decode_top is
function ipbus_sel_top(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
variable sel: ipbus_sel_t;
begin
-- START automatically generated VHDL the Wed Jul 12 14:14:22 2017
if std_match(addr, "---------------------------00---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x00000018
elsif std_match(addr, "---------------------------01---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_I2C, IPBUS_SEL_WIDTH)); -- i2c / base 0x00000008 / mask 0x00000018
elsif std_match(addr, "---------------------------10---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_FREQ_CTR, IPBUS_SEL_WIDTH)); -- freq_ctr / base 0x00000010 / mask 0x00000018
-- END automatically generated VHDL
else
sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
end if;
return sel;
end function ipbus_sel_top;
end ipbus_decode_top;
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