Commit 2a2cf073 authored by Dave Newbold's avatar Dave Newbold

Adding board ID to link idle pattern

parent 14f817df
...@@ -29,8 +29,8 @@ set_property PACKAGE_PIN F6 [get_ports eth_clk_p] ...@@ -29,8 +29,8 @@ set_property PACKAGE_PIN F6 [get_ports eth_clk_p]
set_property PACKAGE_PIN E6 [get_ports eth_clk_n] set_property PACKAGE_PIN E6 [get_ports eth_clk_n]
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hier -filter {name=~infra/eth/*/gtpe2_i}] set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hier -filter {name=~infra/eth/*/gtpe2_i}]
set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells -hier -filter {name=~tlink/mgt_us/*/gtpe2_i}] set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells -hier -filter {name=~tlink/mgt_ds/*/gtpe2_i}]
set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells -hier -filter {name=~tlink/mgt_ds/*/gtpe2_i}] set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells -hier -filter {name=~tlink/mgt_us/*/gtpe2_i}]
proc false_path {patt clk} { proc false_path {patt clk} {
set p [get_ports -quiet $patt -filter {direction != out}] set p [get_ports -quiet $patt -filter {direction != out}]
......
...@@ -24,8 +24,8 @@ set_property PACKAGE_PIN F6 [get_ports eth_clk_p] ...@@ -24,8 +24,8 @@ set_property PACKAGE_PIN F6 [get_ports eth_clk_p]
set_property PACKAGE_PIN E6 [get_ports eth_clk_n] set_property PACKAGE_PIN E6 [get_ports eth_clk_n]
set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hier -filter {name=~infra/eth/*/gtpe2_i}] set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hier -filter {name=~infra/eth/*/gtpe2_i}]
set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells -hier -filter {name=~tlink/mgt_us/*/gtpe2_i}] set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells -hier -filter {name=~tlink/mgt_ds/*/gtpe2_i}]
set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells -hier -filter {name=~tlink/mgt_ds/*/gtpe2_i}] set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells -hier -filter {name=~tlink/mgt_us/*/gtpe2_i}]
proc false_path {patt clk} { proc false_path {patt clk} {
set p [get_ports -quiet $patt -filter {direction != out}] set p [get_ports -quiet $patt -filter {direction != out}]
......
...@@ -217,6 +217,7 @@ begin ...@@ -217,6 +217,7 @@ begin
pllclk => pllclk, pllclk => pllclk,
pllrefclk => pllrefclk, pllrefclk => pllrefclk,
link_ok => link_ok, link_ok => link_ok,
id => board_id,
clk40 => clk40_i, clk40 => clk40_i,
rst40 => rst40_i, rst40 => rst40_i,
d => link_d, d => link_d,
......
...@@ -21,6 +21,7 @@ entity sc_trig_link is ...@@ -21,6 +21,7 @@ entity sc_trig_link is
pllclk: in std_logic; pllclk: in std_logic;
pllrefclk: in std_logic; pllrefclk: in std_logic;
link_ok: out std_logic; link_ok: out std_logic;
id: in std_logic_vector(7 downto 0);
clk40: in std_logic; clk40: in std_logic;
rst40: in std_logic; rst40: in std_logic;
d: in std_logic_vector(15 downto 0); d: in std_logic_vector(15 downto 0);
...@@ -133,6 +134,7 @@ begin ...@@ -133,6 +134,7 @@ begin
ack => '0', ack => '0',
err_i => err_i_us, err_i => err_i_us,
err_o => err_o_us, err_o => err_o_us,
my_id => id,
link_id => id_us link_id => id_us
); );
...@@ -152,6 +154,7 @@ begin ...@@ -152,6 +154,7 @@ begin
ack => '0', ack => '0',
err_i => err_i_ds, err_i => err_i_ds,
err_o => err_o_ds, err_o => err_o_ds,
my_id => id,
link_id => id_ds link_id => id_ds
); );
......
...@@ -23,6 +23,7 @@ entity sc_trig_link_pipe is ...@@ -23,6 +23,7 @@ entity sc_trig_link_pipe is
ack: in std_logic; ack: in std_logic;
err_i: out std_logic; err_i: out std_logic;
err_o: out std_logic; err_o: out std_logic;
my_id: in std_logic_vector(7 downto 0);
link_id: out std_logic_vector(7 downto 0) link_id: out std_logic_vector(7 downto 0)
); );
...@@ -32,9 +33,12 @@ architecture rtl of sc_trig_link_pipe is ...@@ -32,9 +33,12 @@ architecture rtl of sc_trig_link_pipe is
begin begin
txd <= (others => '0'); txd <= X"bc" & my_id;
txk <= "00"; txk <= "10";
q <= (others => '0'); q <= (others => '0');
qv <= '0'; qv <= '0';
err_i <= '0';
err_o <= '0';
link_id <= rxd(7 downto 0);
end rtl; end rtl;
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