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euro-adc-65m-14b-40cha-gw
Commit 261038c6 authored by Dave Newbold's avatar Dave Newbold
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Adding real slaves

parent 5ca2a8b8
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Showing with 118 additions and 18 deletions
projects/timing/addr_table/top.xml
View file @ 261038c6
<node id="TOP">
<node id="io" address="0x0" module="file://pdts_fmc_io.xml"/>
<node id="master" address="0x200" module="file://master.xml"/>
<node id="csr" address="0x0" fwinfo="endpoint;width=1">
<node="ctrl" address="0x0">
<node id="soft_rst" mask="0x1"/>
<node id="nuke" mask="0x2"/>
<node id="rst_mmcm" mask="0x4"/>
<node id="trig" mask="0x8"/>
<node id="sync" mask="0x10"/>
<node id="trig_sel" mask="0x20"/>
<node id="sync_sel" mask="0x40"/>
<node id="busy" mask="0x80"/>
</node>
<node="stat" address="0x1">
<node id="mmcm_locked" mask="0x1"/>
</node>
</node>
<node id="i2c" address="0x8" module="file://opencores_i2c.xml"/>
<node id="freq_ctr" address="0x10" module="file://freq_ctr.xml"/>
</node>
projects/timing/firmware/cfg/payload.dep
View file @ 261038c6
src payload.vhd
#src ipbus_decode_top.vhd
#addrtab -t top.xml
#src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd
src ipbus_decode_top.vhd
addrtab -t top.xml
src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd
src -c ipbus-firmware:components/ipbus_slaves ipbus_ctrlreg_v.vhd
include -c ipbus-firmware:components/opencores_i2c
src sc_timing_iobufs.vhd
#src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
src -c components/mp7_ttc freq_ctr.vhd freq_ctr_div.vhd
addrtab -c components/mp7_ttc freq_ctr.xml
src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_types.vhd
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
projects/timing/firmware/hdl/payload.vhd
View file @ 261038c6
......@@ -5,7 +5,7 @@ use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.ipbus.all;
-- use work.ipbus_decode_top.all;
use work.ipbus_decode_top.all;
entity payload is
port(
......@@ -51,14 +51,77 @@ end payload;
architecture rtl of payload is
-- signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
-- signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal ctrl, stat: ipb_reg_v(0 downto 0);
signal scl, sda_i, sda_o: std_logic;
signal ctrl_trig, ctrl_sync, ctrl_trig_sel, ctrl_sync_sel, ctrl_busy: std_logic;
signal clki, clkdiv: std_logic;
-- attribute IOB: string;
-- attribute IOB of sfp_dout: signal is "TRUE";
begin
-- ipbus address decode
fabric: entity work.ipbus_fabric_sel
generic map(
NSLV => N_SLAVES,
SEL_WIDTH => IPBUS_SEL_WIDTH
)
port map(
ipb_in => ipb_in,
ipb_out => ipb_out,
sel => ipbus_sel_top(ipb_in.ipb_addr),
ipb_to_slaves => ipbw,
ipb_from_slaves => ipbr
);
-- CSR
csr: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => 1,
N_STAT => 5
)
port map(
clk => ipb_clk,
reset => ipb_rst,
ipbus_in => ipbw(N_SLV_CSR),
ipbus_out => ipbr(N_SLV_CSR),
d => stat,
q => ctrl
);
soft_rst <= ctrl(0)(0);
nuke <= ctrl(0)(1);
rst <= ctrl(0)(2);
ctrl_trig <= ctrl(0)(3);
ctrl_sync <= ctrl(0)(4);
ctrl_trig_sel <= ctrl(0)(5);
ctrl_sync_sel <= ctrl(0)(6);
ctrl_busy <= ctrl(0)(7);
-- General IO
userled <= '0';
-- I2C
i2c_analog: entity work.ipbus_i2c_master
port map(
clk => ipb_clk,
rst => ipb_rst,
ipb_in => ipbw(N_SLV_I2C),
ipb_out => ipbr(N_SLV_I2C),
scl => scl,
sda_o => sda_o,
sda_i => sda_i
);
-- Cable IO
bufs: entity work.sc_timing_iobufs
port map(
clk_rstn => '1',
......@@ -67,42 +130,59 @@ begin
clk => '0',
clk_o_p => clk_o_p,
clk_o_n => clk_o_n,
clk_i => open,
clk_i => clki,
clk_i_p => clk_i_p,
clk_i_n => clk_i_n,
trig_o => '0',
trig_o => ctrl_trig_o,
trig_o_p => trig_o_p,
trig_o_n => trig_o_n,
trig_i => open,
trig_i_p => trig_i_p,
trig_i_n => trig_i_n,
sync_o => '0',
sync_o => ctrl_sync_o,
sync_o_p => sync_o_p,
sync_o_n => sync_o_n,
sync_i => open,
sync_i_p => sync_i_p,
sync_i_n => sync_i_n,
trig_sel => '0',
trig_sel => ctrl_trig_sel,
trig_sel_p => trig_sel_p,
trig_sel_n => trig_sel_n,
sync_sel => '0',
sync_sel => ctrl_sync_sel,
sync_sel_p => sync_sel_p,
sync_sel_n => sync_sel_n,
scl => '0',
scl => scl,
scl_p => scl_p,
scl_n => scl_n,
sda_o => '0',
sda_o => sda_o,
sda_o_p => sda_o_p,
sda_o_n => sda_o_n,
sda_i => open,
sda_i => sda_i,
sda_i_p => sda_i_p,
sda_i_n => sda_i_n,
busy_o => '0',
busy_o => ctrl_busy_o,
busy_o_p => busy_o_p,
busy_o_n => busy_o_n,
busy_i => open,
busy_i_p => busy_i_p,
busy_i_n => busy_i_n
);
-- Clock frequency counter
div: entity work.freq_ctr_div
port map(
clk(0) => clki,
clkdiv => clkdiv
);
ctr: entity work.freq_ctr
port map(
clk => clk,
rst => rst,
ipb_in => ipbw(N_SLV_FREQ_CTR),
ipb_out => ipbr(N_SLV_FREQ_CTR),
clkdiv => clkdiv
);
end rtl;
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