Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
E
euro-adc-65m-14b-40cha-gw
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
eurocard
euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
19acfea5
Commit
19acfea5
authored
Aug 24, 2017
by
Dave Newbold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Updating board ID inverter and trigger block
parent
f44284ef
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
3 additions
and
3 deletions
+3
-3
top_pc051b.vhd
boards/pc051b/base_fw/synth/firmware/hdl/top_pc051b.vhd
+1
-1
sc_local_trig.vhd
components/solid/firmware/hdl/sc_local_trig.vhd
+2
-2
No files found.
boards/pc051b/base_fw/synth/firmware/hdl/top_pc051b.vhd
View file @
19acfea5
...
@@ -93,7 +93,7 @@ begin
...
@@ -93,7 +93,7 @@ begin
nuke
=>
nuke
,
nuke
=>
nuke
,
soft_rst
=>
soft_rst
,
soft_rst
=>
soft_rst
,
userleds
=>
leds_c
,
userleds
=>
leds_c
,
addr
=>
addr
,
addr
=>
addr
n
,
sel
=>
sel
,
sel
=>
sel
,
i2c_scl
=>
i2c_scl
,
i2c_scl
=>
i2c_scl
,
i2c_sda_i
=>
i2c_sda_i
,
i2c_sda_i
=>
i2c_sda_i
,
...
...
components/solid/firmware/hdl/sc_local_trig.vhd
View file @
19acfea5
...
@@ -170,12 +170,12 @@ begin
...
@@ -170,12 +170,12 @@ begin
-- Trigger data to readout
-- Trigger data to readout
go
<=
(
go
or
(
ro_go
and
((
or_reduce
(
tc
)
and
not
rveto
)
or
last_gasp
or
hoorah
)))
and
not
blkend
and
en
and
not
rst40
when
rising_edge
(
clk40
);
go
<=
(
go
or
(
ro_go
and
((
or_reduce
(
tc
)
and
not
rveto
)
or
last_gasp
or
hoorah
)))
and
not
blkend
and
en
and
not
rst40
when
rising_edge
(
clk40
);
blkend
<=
'1'
when
unsigned
(
ro_ctr
)
=
3
+
2
*
N_
CHAN_
TRG
else
'0'
;
blkend
<=
'1'
when
unsigned
(
ro_ctr
)
=
3
+
2
*
N_TRG
else
'0'
;
ro_valid
<=
go
;
ro_valid
<=
go
;
ro_blkend
<=
blkend
;
ro_blkend
<=
blkend
;
ch
<=
to_integer
(
unsigned
(
ro_ctr
(
ro_ctr
'length
-
1
downto
1
)));
ch
<=
to_integer
(
unsigned
(
ro_ctr
(
ro_ctr
'length
-
1
downto
1
)));
ch_i
<=
ch
-
2
when
ch
>
1
and
ch
<
N_
CHAN_
TRG
else
0
;
ch_i
<=
ch
-
2
when
ch
>
1
and
ch
<
N_TRG
else
0
;
bi
<=
(
63
downto
N_CHAN
=>
'0'
)
&
cact
(
ch_i
);
bi
<=
(
63
downto
N_CHAN
=>
'0'
)
&
cact
(
ch_i
);
b
<=
bi
(
63
downto
32
)
when
ro_ctr
(
0
)
=
'1'
else
bi
(
31
downto
0
);
b
<=
bi
(
63
downto
32
)
when
ro_ctr
(
0
)
=
'1'
else
bi
(
31
downto
0
);
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment