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masterfip-gw-adam-proposed_master/ 0000775 0000000 0000000 00000000000 13422611646 0017574 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/.gitignore 0000664 0000000 0000000 00000001110 13422611646 0021555 0 ustar 00root root 0000000 0000000 *.bit
*.bin
*.ngc
*~
#*
*.ini
*.log
work
*.vstf
*.wlf
*.version
*.cfg
*.bk
*#
*.bak
run.tcl
.emacs*
.#*
transcript
*.pcf
*.pad
*.ngr
*.ncd
*.gise
*.ptwx
*.twx
*.unroutes
*.ut
*.xpi
*.bgn
*.bld
*.cmd_log
*.drc
*.lso
*.ngd
*.prj
*.stx
*.xst
*_bitgen.xwbt
*_envsettings.html
*_map.map
*_map.ngm
*_map.xrpt
*_ngdbuild.xrpt
*_pad.csv
*_pad.txt
*_par.xrpt
*.xml
*_usage.xml
*_xst.xrpt
xlnx_auto_0_xdb
iseconfig
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pa.fromNcd.tcl
pa.fromNetlist.tcl
planAhead_run_*
*.vcd
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*.elf
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xst/
*stacktrace*
rtl/*.h
scp.sh
disasm.S masterfip-gw-adam-proposed_master/.gitmodules 0000664 0000000 0000000 00000001273 13422611646 0021754 0 ustar 00root root 0000000 0000000 [submodule "ip_cores/wr-node-core"]
path = ip_cores/wr-node-core
url = git://ohwr.org/white-rabbit/wr-node-core.git
[submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
[submodule "ip_cores/nanofip"]
path = ip_cores/nanofip
url = git://ohwr.org/cern-fip/nanofip/nanofip-gateware.git
[submodule "ip_cores/gn4124-core"]
path = ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "ip_cores/wr-cores"]
path = ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "ip_cores/etherbone-core"]
path = ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git masterfip-gw-adam-proposed_master/doc/ 0000775 0000000 0000000 00000000000 13422611646 0020341 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/doc/review_02032017/ 0000775 0000000 0000000 00000000000 13422611646 0022620 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/doc/review_02032017/denia_comments.txt 0000664 0000000 0000000 00000010333 13422611646 0026346 0 ustar 00root root 0000000 0000000 masterFIP review comments:
General comments:
==================
- Very readable code, useful comments, and very useful diagrams at the top.
- Repo seems to be in good order.
- Most processes are missing the p_ prefix.
- Optionally, use the name of the process at the end, i.e.: end process p_process_name.
- Indentation at some places needs to be corrected.
fmc_massterFIP_core.vhd
========================
- Line 517, 534 and 549: Expression core_rst = '1' or rx_rst = '1' used in 3 places.
Use one signal assignement and use that instead for optimisation.
- Same for core_rst_n = '0' or fd_host_rst = '1' which is used in various places.
- Some indentation may be improved, eg in: cmp_masterfip_tx.
- fd_wdgn signal should be renamed fd_wdg_n, same for fd_rstn_o-> fd_rst_n_o
- I know chipscope is commented, but, the port map has the wrong syntax
(<= instead of => and the semicolons at the end)
masterfip_tx:
=============
- I found the suffixes to express 1-tick delays a little confusing. You
have in the same process:
line 304 last_data_byte_p_d <= last_data_byte_p_tmp;
last_data_byte_p <= last_data_byte_p_d;
And this:
line 307
byte_request_accept_p_d1 <= byte_request_accept_p_tmp;
byte_request_accept_p_d2 <= byte_request_accept_p_d1;
Why not use the same suffix scheme? preferably use "_dn" for both sets of expressions,
in agreement with VHDL guidelines table 3 p12. "_tmp" can be replaced by
"_d0"?
masterfip_rx:
=============
- s_ suffix for signals is optional. I think its use is especially
redundant since it is not used for all the signals in this module.
- Line 270: create_32bit_words process name should have the p_ prefix.
- Line 300: use p_ prefix for process name
- Line 263: bytes_c_rst expression:
bytes_c_rst <= '1' when (rst_i = '1' or rx_rst_i = '1') else '0';
effectively means that bytes_c_rst is the same value as (rst_i = '1' or rx_rst_i = '1').
Make it as an assignement (?)
bytes_c_rst <= rst_i or rx_rst_i;
- The expression (rst_i = '1' or rx_rst_i = '1') is evaluated at 4
separate occasions. Would it be better to assign it to a signal and
perform the OR only once? (ties in with previous remark).
- In process data_transfer_to_regs:
- add p_ prefix to process name.
- The operation: word32_num <= word32_num + 1;
seems to be performed no matter what the condition is (apart from reset condition)
could be performed once straight after the first else?
- In...
.....
if word32_num = 0 then
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
elsif (unsigned(rx_byte_index)-2) mod 4 = 3 then -- [CRC|CRC|BYTE|BYTE]
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
.....
It looks like the two conditions could be grouped under one condition
with an OR as the outcome is the same. In fact, it seems that most
outcomes are the same apart from Line 338. It seems the code could be
much more compact.
leds_manager.vhd
=================
Could this core be made more generic by removing all the TDC-specific
references in comments and port names and moved inside general core ?
- Line 96: add prefix g_ for generic values_for_simul
- In process pulse_generator, all acam_channel(2 downto 0) values other
than 0, 1, 2, 3 result in ch5 LED being lit. Is this okay functionally?
Wouldn it better to add the "="100" condition and send all the other
possibilities to the final else statement (all channels off?)
decr_counter.vhd
=================
- Use c_ prefix for constants.
- Couldn't signal one <= zeroes + "1" be made into a constant, something like:
constant c_one : unsigned (width-1 downto 0):= to_unsigned (1, width-1) (?)
- Is counter_is_zero_o supposed to be 1-tick long? if so add _p suffix,
else it could be assigned outside the process like this?
counter_is_zero_o <= '1' when counter = zeroes else "0";
- Also seems like since decrement operation is present in most
conditions, the code could be made more compact.
incr_counter.vhd
=================
- s_counter does not need prefix.
masterfip-gw-adam-proposed_master/doc/review_02032017/dlamprid_comments.html 0000664 0000000 0000000 00000026474 13422611646 0027224 0 ustar 00root root 0000000 0000000
Comments for masterFIP GW review <2017-03-16 Thu>
Comments for masterFIP GW review <2017-03-16 Thu>
1 Project/Synthesis/PAR
- [+] 3943 warnings during synthesis
- [+] ucf: "TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback" points to non-existing
node 'U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback'.
[-]
120+ warnings about missing/duplicates files when we first open the .xise project file, and
the messages keep reappearing while we use the tool
[-]
Project hierarchy shows too many unused files (not under spec_masterfip_mt entity)
[-]
running hdlmake in syn/spec does not work
[-]
many (~50) synthesis-generated files not git-ignored
[-]
if not a build script for wbgen, at least a README with how you expect the wbgen2 command to
be invoked should be provided
2 Simulation
- [!] Error: (vcom-19) Failed to access library 'nanofip_lib' at "nanofip_lib" (Modelsim SE-64
10.2a, Linux) This is due to case-sensitivity in Linux. Solution: replace "vlib nanoFIP_lib"
with "vlib nanofip_lib" or, alternatively, replace "vcom -work nanofip_lib" with "vcom -work
nanoFIP_lib"
- [!] Error: (vcom-7) Failed to open design unit file "../../sim/spec/testbench/nanofip_lib/*" in
read mode. Again, this is due to case-sensitivity in Linux, since the folder commited in git is
actually sim/spec/testbench/nanoFIP_lib
- [+] Trying to step into the code with Modelsim produces: Error opening
/opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/unisims/primitive/PLL_ADV.vhd. This path does not exist in
my system.
- [+] Fix warnings "numeric_std.to_integer metavalue detected, returning 0" (alternatively, use
"set NumericStdNoWarnings 1" after the call to vsim in your do files, suboptimal solution because
it might also hide useful metavalue warnings)
[-]
After clearing the metavalue warnings, have a look also at the remaining warnings
[-]
Some signals are always 'X', if they are not useful in simulation, just remove them
[-]
group signal waveforms
[-]
split compilation (vcom) from running in separate "do" files, invoke them both from a top do
file (eg. compile.do + run.do => sim.do)
[-]
many (~100) simulation-generated files not git-ignored
- [?] Do you need the "vlog $env(XILINX)/verilog/src/glbl.v"? If not, remove it, otherwise users
might get the error "can't read "env(XILINX)": no such variable" if they haven't set this
environment variable.
3 Design
- [?] rtl: is leds_manager.vhd used at all? what about carrier_info.vhd, free_counter.vhd, and
perhaps others? If not, it's better to delete them from the repository.
- [?] rtl: why is wf_package.vhd declared here AND in ip-cores/nanofip?
- [?] top: is synthesis_descriptor.vhd used?
- [*] the whole nanofip as ip-core of masterfip seems a bit counter-intuitive. If there are things
used by both, the should belong to a "fip" project, and both nano- and master- should use them.
3.1 masterFIP_pkg
[-]
constants should have lower case "c" (I think)
3.2 spec_masterfip_mt
3.2.1 fmc_masterFIP_core
[-]
it would be nice to have a bit more hierachy in this module, with less low-level processes
and modules lying around (eg. counter modules, assignments to wb registers) , to highlight the
high-level structure of the core.
- [?] why do you use two decreasing counter modules (wf_decr_counter and decr_counter)?
- [?] why is speed_X_i not a 2-bit vector?
- [?] would it be interesting for diagnostics to monitor if/when counters overflow?
- [?] why is reg_to_mt.fd_wdg_tstamp_i one bit larger than macrocyc_cnt?
- [*] cmp_ext_sync_deglitch_p_detect and cmp_fd_wdgn_deglitch_p_detect introduce one unnecessary
FF/latency cycle
- [*] we should introduce generic up/down counters to general-cores
- masterfip_tx
[-]
synch_signals process could be replaced by 2x gc_sync_ffs
- [?] more importantly, why do you resync these two signals?
- masterfip_rx
- [?] can't you use general-cores for cmp_rx_deglitcher? (perhaps think about it also in nanofip
project)
- [?] did you make up your mind about what to connect to nfip_rst_i port of cmp_rx_deglitcher? if
yes, remove the inline comment
4 Legend
- [!] = fatal
- [+] = important
[-]
= minor
- [?] = question
- [*] = note
Author: Dimitrios Lampridis
Created: 2017-03-16 Thu 12:14
Emacs 24.5.1 (Org mode 8.2.10)
Validate
masterfip-gw-adam-proposed_master/doc/review_02032017/dlamprid_comments.org 0000664 0000000 0000000 00000010404 13422611646 0027031 0 ustar 00root root 0000000 0000000 # emacs org-mode options and definitions, just ignore
#+OPTIONS: toc:nil
#+OPTIONS: ^:nil
#+TITLE: Comments for masterFIP GW review <2017-03-16 Thu>
* Project/Synthesis/PAR
- [+] 3943 warnings during synthesis
- [+] ucf: "TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback" points to non-existing
node 'U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback'.
- [-] 120+ warnings about missing/duplicates files when we first open the .xise project file, and
the messages keep reappearing while we use the tool
- [-] Project hierarchy shows too many unused files (not under spec_masterfip_mt entity)
- [-] running hdlmake in syn/spec does not work
- [-] many (~50) synthesis-generated files not git-ignored
- [-] if not a build script for wbgen, at least a README with how you expect the wbgen2 command to
be invoked should be provided
* Simulation
- [!] Error: (vcom-19) Failed to access library 'nanofip_lib' at "nanofip_lib" (Modelsim SE-64
10.2a, Linux) This is due to case-sensitivity in Linux. Solution: replace "vlib nanoFIP_lib"
with "vlib nanofip_lib" or, alternatively, replace "vcom -work nanofip_lib" with "vcom -work
nanoFIP_lib"
- [!] Error: (vcom-7) Failed to open design unit file "../../sim/spec/testbench/nanofip_lib/*" in
read mode. Again, this is due to case-sensitivity in Linux, since the folder commited in git is
actually sim/spec/testbench/nanoFIP_lib
- [+] Trying to step into the code with Modelsim produces: Error opening
/opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/unisims/primitive/PLL_ADV.vhd. This path does not exist in
my system.
- [+] Fix warnings "numeric_std.to_integer metavalue detected, returning 0" (alternatively, use
"set NumericStdNoWarnings 1" after the call to vsim in your do files, suboptimal solution because
it might also hide useful metavalue warnings)
- [-] After clearing the metavalue warnings, have a look also at the remaining warnings
- [-] Some signals are always 'X', if they are not useful in simulation, just remove them
- [-] group signal waveforms
- [-] split compilation (vcom) from running in separate "do" files, invoke them both from a top do
file (eg. compile.do + run.do => sim.do)
- [-] many (~100) simulation-generated files not git-ignored
- [?] Do you need the "vlog $env(XILINX)/verilog/src/glbl.v"? If not, remove it, otherwise users
might get the error "can't read "env(XILINX)": no such variable" if they haven't set this
environment variable.
* Design
- [?] rtl: is leds_manager.vhd used at all? what about carrier_info.vhd, free_counter.vhd, and
perhaps others? If not, it's better to delete them from the repository.
- [?] rtl: why is wf_package.vhd declared here AND in ip-cores/nanofip?
- [?] top: is synthesis_descriptor.vhd used?
- [*] the whole nanofip as ip-core of masterfip seems a bit counter-intuitive. If there are things
used by both, the should belong to a "fip" project, and both nano- and master- should use them.
** masterFIP_pkg
- [-] constants should have lower case "c" (I think)
** spec_masterfip_mt
*** fmc_masterFIP_core
- [-] it would be nice to have a bit more hierachy in this module, with less low-level processes
and modules lying around (eg. counter modules, assignments to wb registers) , to highlight the
high-level structure of the core.
- [?] why do you use two decreasing counter modules (wf_decr_counter and decr_counter)?
- [?] why is speed_X_i not a 2-bit vector?
- [?] would it be interesting for diagnostics to monitor if/when counters overflow?
- [?] why is reg_to_mt.fd_wdg_tstamp_i one bit larger than macrocyc_cnt?
- [*] cmp_ext_sync_deglitch_p_detect and cmp_fd_wdgn_deglitch_p_detect introduce one unnecessary
FF/latency cycle
- [*] we should introduce generic up/down counters to general-cores
**** masterfip_tx
- [-] synch_signals process could be replaced by 2x gc_sync_ffs
- [?] more importantly, why do you resync these two signals?
**** masterfip_rx
- [?] can't you use general-cores for cmp_rx_deglitcher? (perhaps think about it also in nanofip
project)
- [?] did you make up your mind about what to connect to nfip_rst_i port of cmp_rx_deglitcher? if
yes, remove the inline comment
* Legend
- [!] = fatal
- [+] = important
- [-] = minor
- [?] = question
- [*] = note
masterfip-gw-adam-proposed_master/doc/review_02032017/evaG_comments.txt 0000664 0000000 0000000 00000000000 13422611646 0026136 0 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/ip_cores/ 0000775 0000000 0000000 00000000000 13422611646 0021377 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/ip_cores/etherbone-core/ 0000775 0000000 0000000 00000000000 13422611646 0024300 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/ip_cores/general-cores/ 0000775 0000000 0000000 00000000000 13422611646 0024125 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/ip_cores/gn4124-core/ 0000775 0000000 0000000 00000000000 13422611646 0023244 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/ip_cores/nanofip/ 0000775 0000000 0000000 00000000000 13422611646 0023031 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/ip_cores/wr-cores/ 0000775 0000000 0000000 00000000000 13422611646 0023140 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/ip_cores/wr-node-core/ 0000775 0000000 0000000 00000000000 13422611646 0023700 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/rtl/ 0000775 0000000 0000000 00000000000 13422611646 0020375 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/rtl/decr_counter.vhd 0000664 0000000 0000000 00000015050 13422611646 0023555 0 ustar 00root root 0000000 0000000 --_________________________________________________________________________________________________
-- |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- decr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File decr_counter.vhd |
-- |
-- Description Stop counter. Configurable "counter_top_i" and "width". |
-- "Current count value" and "counting done" signals available. |
-- "Counter done" signal asserted simultaneous to "current count value = 0". |
-- Countdown is launched each time "counter_load_i" is asserted for one clock tick. |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
-- Entity declaration for decr_counter
--=================================================================================================
entity decr_counter is
generic
(width : integer := 32); -- default size
port
-- INPUTS
(clk_i : in std_logic;
rst_i : in std_logic;
counter_load_i : in std_logic; -- loads counter with counter_top_i
counter_top_i : in std_logic_vector(width-1 downto 0); -- counter start value
-- OUTPUTS
counter_o : out std_logic_vector(width-1 downto 0);
counter_is_zero_o : out std_logic); -- counter empty indication
end decr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of decr_counter is
constant zeroes : unsigned(width-1 downto 0) :=(others=>'0');
signal one : unsigned(width-1 downto 0);
signal counter : unsigned(width-1 downto 0) := (others=>'0'); -- init to avoid sim warnings
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
decr_counting: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
counter_is_zero_o <= '0';
counter <= zeroes;
elsif counter_load_i = '1' then
counter_is_zero_o <= '0';
counter <= unsigned(counter_top_i) - "1";
elsif counter = zeroes then
counter_is_zero_o <= '0';
counter <= zeroes;
elsif counter = one then
counter_is_zero_o <= '1';
counter <= counter - "1";
else
counter_is_zero_o <= '0';
counter <= counter - "1";
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= std_logic_vector(counter);
one <= zeroes + "1";
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- masterfip-gw-adam-proposed_master/rtl/fmc_masterFIP_core.vhd 0000664 0000000 0000000 00000155627 13422611646 0024607 0 ustar 00root root 0000000 0000000 --_________________________________________________________________________________________________
-- |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- fmc_masterFIP_core |
-- |
---------------------------------------------------------------------------------------------------
-- File fmc_masterFIP_core.vhd |
-- |
-- Description The masterFIP_core instantiates all the modules needed to establish WorldFIP |
-- communication. Figure 1 shows the modules of the core. |
-- There is only one clock domain in the core. |
-- |
-- _ ________________________________________________________________ |
-- |F| | fmc_masterFIP_core | |
-- |I| | _________________ ____________ ____________ ______ | |
-- |E| | | | | MACROCYCLE | | SILENCE | | | | |
-- |L| <--| | TX | | TIME CNT | | TIME CNT | | | | |
-- |D| | _________________| |____________| |____________| | | | |
-- |R| | _________________ ____________ ____________ | | | |
-- |I| -->| | | | TURNAROUND | | | | | | |
-- |V| | | RX | | TIME CNT | | RESETS | | | | |
-- |E| | |_________________| |____________| |____________| |WBGEN2| | <-processor-> |
-- |_| | | CSR | | |
-- | _________________ | | | |
-- sync pulse -->| | EXT SYNC PULSE | | | | |
-- | |_________________| | | | |
-- | ___________ | | | |
-- DS18B20 <-->| | ONEWIRE | | | | |
-- | |___________| | | | |
-- | ______ | | | |
-- LEDs <--| | LEDs | | | | |
-- | |______| |______| | |
-- |________________________________________________________________| |
-- Figure 1: fmc_masterFIP_core architecture |
-- |
-- MASTERFIP WBGEN2 CSR: |
-- The masterfip_wbgen2_csr module has been generated through the wbgen2 application.|
-- It establishes the interface with the processor, usually a Mock Turtle core. |
-- This interface contains a set of control and status registers for each one of the |
-- units of Figure 1; it also contains the WorldFIP frame PAYLOAD data for the TX |
-- and RX. Regarding the PAYLOAD data, it was decided not to use a FIFO for passing |
-- the WorldFIP PAYLOAD data from the processor to this core for serialization or for|
-- passing the WorldFIP PAYLOAD data that have been deserialized from this core to |
-- the processor. Instead a set of 67 32-bit-registers (= 268 bytes, which is the max|
-- WorldFIP frame size) is used for each of the TX and RX; like this the time for |
-- which the data need to remain static to be read is minimized, leading to a simpler|
-- design. |
-- |
-- MASTERFIP TX: |
-- The masterfip_tx places a complete WorldFIP frame on the WorldFIP bus. |
-- The masterfip_tx ignores the frame type (ID_DAT/RT_DAT/RP_MSG etc..), or the |
-- macrocycle sequence and macrocycle timing; the processor (MT) is responsible for |
-- managing all these aspects and for providing to the masterfip_tx the bytes to |
-- serialise, along with a start pulse. |
-- The communication between the processor and the masterfip_tx is handled through a |
-- set of control (from the MT) and status (from the masterfip_tx) signals/registers |
-- defined in the masterfip_wbgen2_csr module. |
-- Upon a rising edge on the tx_ctrl_start pulse, the masterfip_tx: |
-- - copies all the payload registers (tx_payld_ctrl, tx_payld_reg1..tx_payld_reg67)|
-- and the register that indicates the number of payload bytes to |
-- serialize (tx_ctrl_bytes_num) |
-- - starts serializing a WorldFIP frame (see following Figure). Note that the FSS, |
-- CRC and FES fields are generated internally in the masterfip_tx unit. |
-- - after the FES, rises the tx_stat_stop status bit to signal to the MT the end |
-- of a successful frame transmission. |
-- ______________________________________________________________________________ |
-- |_____FSS_____|__Ctrl__|_____________tx_payld_____________|_____CRC____|__FES__| |
-- |
-- <---2 bytes--><-1byte-><------ tx_ctrl_bytes_num -------><--2 bytes--><-1byte-> |
-- |
-- Figure 2: WorldFIP tx frame structure |
-- |
-- MASTERFIP RX: |
-- The masterfip_rx retrieves a WorldFIP frame from the WorldFIP bus. |
-- Similar to the masterfip_tx, the masterfip_rx has no intelligence regarding the |
-- macrocycle sequence; it is controlled and monitored by the processor (MT) through |
-- the masterfip_wbgen2_csr, where a set of control and status registers are defined.|
-- As long as it is not under reset, the masterfip_rx is probing the WorldFIP bus |
-- trying to identify the FSS sequence of a WorldFIP frame. It signals the FSS |
-- detection to the processor through the status bit rx_stat_pream_ok and continues |
-- deserializing the rest of the frame. It stores the first byte after the FSS to the|
-- rx_payld_ctrl register and the rest of the bytes to the registers |
-- rx_payld_reg1..rx_payld_reg67. Upon the detection of a FES the masterfip_rx |
-- checks the CRC of the frame and enables the status bit rx_stat_frame_ok or |
-- rx_stat_crc_err accordingly. Upon the rx_stat_frame_ok, the status register |
-- rx_stat_bytes_num indicates the number of bytes in the frame (this indicates |
-- the number of rx_payld_regs and the number of bytes inside the last rx_payld_reg |
-- to be retrieved by the processor). |
-- The processor should copy the rx_payld_regs upon a rx_stat_frame_ok; the regs |
-- keep their values until a rx_rst or until the detection of a new rx_stat_frame_ok.|
-- This time, in the worst case (bit rate 2.5 Mbps) can be calculated as: |
-- (Min Turnaround time of a node = 4 us) + (RP_FIN duration = 19.2 us) = 23.2 us |
-- ______________________________________________________________________________ |
-- |_____FSS_____|__Ctrl__|_____________rx_payld_____________|_____CRC____|__FES__| |
-- |
-- <---2 bytes--><-1byte-><------ rx_ctrl_bytes_num -------><--2 bytes--><-1byte-> |
-- |
-- Figure 3: WorldFIP rx frame structure |
-- |
-- EXT SYNC PULSE: |
-- The modules related to the ext_sync_pulse, synchronise, deglitch and count the |
-- number of rising-edge pulses that arrive to the ext_sync input of the board; |
-- they provide the result to a dedicated masterfip_wbgen2_csr register. |
-- |
-- MACROCYCLE: |
-- The modules related to the macrocycle, count the time of a macrocycle using the |
-- 10 ns input clock as well as the number of macrocycles since startup/a reset. |
-- Dedicated registers in the masterfip_wbgen2_csr provide the counters values |
-- to the processor (MT). Note that the duration/length of the macrocycle comes |
-- from the processor through another dedicated register in the masterfip_wbgen2_csr |
-- that should be set once in the application startup. |
-- |
-- TURNAROUND, SILENCE TIMES: |
-- The modules related to the turnaround and silence time, count the respective time |
-- using the 10 ns clock. Dedicated regs in the masterfip_wbgen2_csr provide the |
-- counters values to the processor (MT). As in the case of the macrocycle length, |
-- the turnaround and silence time length is provided through other dedicated regs in|
-- the masterfip_wbgen2_csr that should be set once in the application startup. |
-- |
-- ONEWIRE: |
-- The DS18B20 module is for the 1-wire reading of the unique ID and temperature on |
-- the mezzanine. Differently than in other designs that implement sw-bit-banging, |
-- here the communication is hard-coded in vhdl, so as to simplify the drivers. |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.masterfip_wbgen2_pkg.all;
use work.masterfip_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.genram_pkg.all;
use work.wf_package.all;
--=================================================================================================
-- Entity declaration for fmc_masterFIP_core
--=================================================================================================
entity fmc_masterFIP_core is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_simul : boolean := FALSE); -- set to TRUE when instantiated in a test-bench
port
(-- Clock and reset
clk_i : in std_logic; -- only one clk domain
rst_n_i : in std_logic; -- PCIe reset, synched with the clk_i
-- Bus Speed -- 31.25 Kbps: speed_b1 = 0, speed_b0 = 0
speed_b0_i : in std_logic; -- 1 Mbps : speed_b1 = 0, speed_b0 = 1
speed_b1_i : in std_logic; -- 2.5 Mbps : speed_b1 = 1, speed_b0 = 0
-- 5 Mbps : speed_b1 = 1, speed_b0 = 1
-- One wire DS18B20U+ on the mezzanine
onewire_b : inout std_logic; -- temper and unique id
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enables the 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_n_o : out std_logic; -- transceiver output enable negative
ext_sync_a_i : in std_logic; -- sync pulse
-- FielDrive interface
fd_rstn_o : out std_logic; -- reset
fd_rxcdn_a_i : in std_logic; -- rx carrier detect
fd_rxd_a_i : in std_logic; -- rx data
fd_wdgn_a_i : in std_logic; -- tx watchdog
fd_txer_a_i : in std_logic; -- tx error
fd_txck_o : out std_logic; -- tx clk
fd_txd_o : out std_logic; -- tx data
fd_txena_o : out std_logic; -- tx enable
-- WISHBONE classic bus interface with the processor (MT)
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stall_o : out std_logic;
wb_ack_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0);
-- LEDs and debugging signals to pass to the higher levels
leds_o : out std_logic_vector(g_width-1 downto 0));
end fmc_masterFIP_core;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of fmc_masterFIP_core is
-- wbgen2 regs from/to mock turtle
signal reg_to_mt : t_masterfip_in_registers;
signal reg_from_mt : t_masterfip_out_registers;
-- resets
signal rst_n, core_rst, core_rst_n : std_logic;
signal fd_host_rst : std_logic;
signal extend : std_logic_vector(c_PERIODS_COUNTER_LGTH-1 downto 0);
-- config
signal speed : std_logic_vector(1 downto 0);
-- ext pulse
signal ext_sync, ext_sync_p, ext_sync_oe : std_logic;
signal ext_sync_p_cnt_rst : std_logic;
signal macroc_close_to_end : std_logic;
signal ext_sync_safe_p, ext_sync_filt : std_logic;
signal ext_sync_p_cnt : std_logic_vector(g_width-1 downto 0);
-- counters
signal macrocyc_load_p, turnar_load_p : std_logic;
signal num_of_macrocyc_cnt_full : std_logic;
signal num_of_macrocyc_cnt : std_logic_vector(g_width-1 downto 0);
signal num_of_macrocyc_cnt_reinit : std_logic;
signal macrocyc_cnt : std_logic_vector(g_width-2 downto 0);
signal macrocyc_cnt_zero_p, silen_load_p : std_logic;
-- tx
signal tx_completed_p, tx_completed : std_logic;
signal tx_rst, fd_txd, fd_txck : std_logic;
signal tx_frame : tx_frame_t;
-- rx
signal rx_rst : std_logic;
signal rx_fss_received_p, rx_fss_received : std_logic;
signal rx_frame_ok_p, rx_frame_ok : std_logic;
signal rx_crc_wrong, rx_byte_ready_p : std_logic;
signal rx_crc_wrong_p, fd_txena : std_logic;
signal rx_frame : rx_frame_t;
signal rx_byte : std_logic_vector(C_BYTE_WIDTH-1 downto 0);
signal rx_byte_index : std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
-- fd_wdgn, fd_txer, fd_rxcdn
signal fd_wdg_tstamp, fd_txer_tstamp : std_logic_vector(30 downto 0);
signal fd_wdgn, fd_wdg, fd_wdg_p, fd_rxcd : std_logic;
signal fd_rxcdn, fd_txer_cnt_reinit : std_logic;
signal fd_txer, fd_txer_filt, fd_txer_p : std_logic;
-- one wire
signal tmp_temper : std_logic_vector(15 downto 0);
signal tmp_id : std_logic_vector(63 downto 0);
signal onewire_read_p, pps_is_zero : std_logic;
signal pps_load_p : std_logic;
-- chipscope
-- component chipscope_ila
-- port (
-- CONTROL : inout std_logic_vector(35 downto 0);
-- CLK : in std_logic;
-- TRIG0 : in std_logic_vector(31 downto 0);
-- TRIG1 : in std_logic_vector(31 downto 0);
-- TRIG2 : in std_logic_vector(31 downto 0);
-- TRIG3 : in std_logic_vector(31 downto 0));
-- end component;
-- component chipscope_icon
-- port (CONTROL0 : inout std_logic_vector(35 downto 0));
-- end component;
-- signal CONTROL : std_logic_vector(35 downto 0);
-- signal CLK : std_logic;
-- signal TRIG0 : std_logic_vector(31 downto 0);
-- signal TRIG1 : std_logic_vector(31 downto 0);
-- signal TRIG2 : std_logic_vector(31 downto 0);
-- signal TRIG3 : std_logic_vector(31 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- speed --
---------------------------------------------------------------------------------------------------
speed <= speed_b1_i & speed_b0_i;
reg_to_mt.speed_i <= speed;
---------------------------------------------------------------------------------------------------
-- RESETS --
---------------------------------------------------------------------------------------------------
core_rst <= reg_from_mt.rst_core_o or (not rst_n_i); -- reset from MT OR PCIe reset
core_rst_n <= not core_rst;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FIELDRIVE rst: generation of a pulse 1 x WorldFIP-clk-cycles long
cmp_fd_rst_generate: gc_dyn_extend_pulse
generic map(g_len_width => c_PERIODS_COUNTER_LGTH)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => reg_from_mt.rst_fd_o, -- monostable: 1-clk-tick-long pulse
len_i => extend,
extended_o => fd_host_rst);
extend <= std_logic_vector(c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(speed))));
fd_rstn_o <= not fd_host_rst;
---------------------------------------------------------------------------------------------------
-- WBGEN2 REGS FROM/TO MOCK TURTLE --
---------------------------------------------------------------------------------------------------
cmp_masterfip_csr: masterfip_wbgen2_csr
port map
(rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i(9 downto 2),
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o,
regs_i => reg_to_mt,
regs_o => reg_from_mt);
---------------------------------------------------------------------------------------------------
-- EXT SYNC PULSE --
---------------------------------------------------------------------------------------------------
ext_sync_dir_o <= reg_from_mt.ext_sync_ctrl_dir_o;
ext_sync_oe_n_o <= reg_from_mt.ext_sync_ctrl_oe_n_o;
ext_sync_term_en_o <= reg_from_mt.ext_sync_ctrl_term_en_o;
-- input synchronizer of the ext_sync_a_i signal
cmp_ext_sync_sync: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => ext_sync_a_i,
synced_o => ext_sync);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_ext_sync_deglitch: gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
port map -- Note that the filter adds a 100 ns delay to the ext_sync signal
(clk_i => clk_i,
rst_n_i => core_rst_n,
dat_i => ext_sync,
dat_o => ext_sync_filt);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- rising edge detection on the deglitched signal
cmp_ext_sync_deglitch_p_detect: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => ext_sync_filt,
ppulse_o => ext_sync_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter of the number of rising edges
cmp_ext_sync_p_cnt:incr_counter
generic map(g_counter_lgth => 32) -- for the fastest macrocycle of 20ms, the counter
-- can keep counting for 2.7 years
port map
(clk_i => clk_i,
counter_incr_i => ext_sync_p,
counter_reinit_i => ext_sync_p_cnt_rst,
counter_o => reg_to_mt.ext_sync_p_cnt_i);
-- -- -- -- -- -- -- -- -- -- --
ext_sync_p_cnt_rst <= reg_from_mt.ext_sync_ctrl_p_cnt_rst_o or core_rst;
---------------------------------------------------------------------------------------------------
-- MACROCYCLE COUNTER --
---------------------------------------------------------------------------------------------------
-- Regarding synchronisation, the masterFIP application can work in three modes:
-- 1) using an internal counter that counts each macrocycle based on the SPEC local oscillator;
-- this mode is active based on the state of the transceiver signal ext_sync_ctrl_oe_n_o.
-- 2) using the ext_sync pulse to signal the beginning of each macrocycle
-- 3) using the ext_sync pulse to signal the beginning of each macrocycle together with an input
-- from the processor indicating that all the periodic traffic has been completed and the processor
-- is ready to start a new macrocycle.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the macrocycle time;
-- the macrocycle length (counter top) should be set once upon the application startup
cmp_macrocycle_time_cnt: decr_counter
generic map(width => g_width-1)
port map
(clk_i => clk_i,
rst_i => core_rst,
counter_load_i => macrocyc_load_p,
counter_top_i => reg_from_mt.macrocyc_lgth_o,
counter_o => macrocyc_cnt,
counter_is_zero_o => macrocyc_cnt_zero_p);
-- -- -- -- -- -- -- -- -- -- --
reg_to_mt.macrocyc_time_cnt_i <= macrocyc_cnt;
macrocyc_load_p <= macrocyc_cnt_zero_p or reg_from_mt.macrocyc_start_o when reg_from_mt.ext_sync_ctrl_oe_n_o = '1' -- internal counting
else ext_sync_p when reg_from_mt.ext_sync_ctrl_oe_n_o = '0' and reg_from_mt.ext_sync_ctrl_opt_o = '0' -- pure external control
else ext_sync_p and reg_from_mt.ext_sync_ctrl_safe_wind_o; -- macrocycle restart, based on macrocycle execution
-- note: macrocyc_start_o is a monostable, 1-clk-tick-long pulse
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the number of macrocycles;
-- being a 32-bit counter, for the fastest application of 20 ms macrocycle, the counter can
-- keep counting for 2.7 years; when it fills up it would restart from 0.
cmp_macrocycles_cnt: incr_counter
generic map(g_counter_lgth => g_width)
port map
(clk_i => clk_i,
counter_incr_i => macrocyc_cnt_zero_p,
counter_reinit_i => num_of_macrocyc_cnt_reinit,
counter_is_full_o => num_of_macrocyc_cnt_full,
counter_o => reg_to_mt.macrocyc_num_cnt_i);
-- -- -- -- -- -- -- -- -- -- --
num_of_macrocyc_cnt_reinit <= core_rst or num_of_macrocyc_cnt_full;
---------------------------------------------------------------------------------------------------
-- TURNAROUND COUNTER --
---------------------------------------------------------------------------------------------------
-- counter counting the turnaround time i.e. the time after the end of transmission of a frame
-- (tx_completed_p), or after the end of reception of a frame (rx_frame_ok_p/ rx_crc_wrong_p)
-- and before the transmission of a new frame.
-- turnaround counter
cmp_turnaround_cnt: decr_counter
generic map(width => 31)
port map
(clk_i => clk_i,
rst_i => core_rst,
counter_load_i => turnar_load_p,
counter_top_i => reg_from_mt.turnar_lgth_o,
counter_o => reg_to_mt.turnar_time_cnt_i,
counter_is_zero_o => open); -- too fast to be used by MT
-- -- -- -- -- -- -- -- -- -- --
turnar_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or reg_from_mt.turnar_start_o;
-- note: turnar_start_o is a monostable, 1-clk-tick-long pulse
---------------------------------------------------------------------------------------------------
-- SILENCE COUNTER --
---------------------------------------------------------------------------------------------------
-- counter counting the silence time i.e. the maximum amount of time that the masterFIP waits for
-- a response frame; the counting starts after the transmission of a frame sent by the master
-- (tx_completed_p) or after the reception of a frame (rx_frame_ok_p/ rx_crc_wrong_p) for the
-- case of a RP_DAT_MSG that would be followed by RP_FIN.
cmp_silence_cnt: decr_counter
generic map(width => 31)
port map
(clk_i => clk_i,
rst_i => core_rst,
counter_load_i => silen_load_p,
counter_top_i => reg_from_mt.silen_lgth_o,
counter_o => reg_to_mt.silen_time_cnt_i,
counter_is_zero_o => open); -- too fast to be used by MT
-- -- -- -- -- -- -- -- -- -- --
silen_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or reg_from_mt.silen_start_o;
-- note: turnar_start_o is a monostable, 1-clk-tick-long pulse
---------------------------------------------------------------------------------------------------
-- MASTERFIP RX --
---------------------------------------------------------------------------------------------------
-- Note that the deglitching of the fd_rxd_a_i takes place inside the masterfip_rx unit.
cmp_masterfip_rx: masterfip_rx
port map
(clk_i => clk_i,
rst_i => core_rst,
rx_rst_i => rx_rst, -- reset from the MT or reset while transmitting
speed_i => speed,
rx_d_a_i => fd_rxd_a_i,
rx_byte_index_o => rx_byte_index, -- current byte index
rx_word_index_o => reg_to_mt.rx_stat_curr_word_indx_i(C_FRAME_WORDS_CNT_LGTH-1 downto 0),
rx_ctrl_byte_o => reg_to_mt.rx_payld_ctrl_i,
rx_ctrl_byte_ok_o => reg_to_mt.rx_stat_ctrl_byte_ok_i,
rx_frame_o => rx_frame,
rx_fss_crc_fes_ok_p_o => rx_frame_ok_p,
rx_fss_received_p_o => rx_fss_received_p,
rx_crc_wrong_p_o => rx_crc_wrong_p,
rx_bytes_num_err_o => reg_to_mt.rx_stat_bytes_num_err_i,
rx_byte_o => rx_byte, -- for debugging
rx_byte_ready_p_o => rx_byte_ready_p);-- for debugging
---------------------------------------------------------------------------------------------------
-- Signals for the RX --
---------------------------------------------------------------------------------------------------
-- The receiver RX is disabled when a frame is being transmitted (fd_txena active).
-- Note that the reg_from_mt.rx_ctrl_rst_o is a monostable, 1-clk-tick-long pulse
rx_rst <= reg_from_mt.rx_ctrl_rst_o or fd_txena;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- registering the number of received bytes upon rx_frame_ok_p; the final number does not include
-- FSS, CTRL, CRC and FES bytes.
p_rx_bytes_num : process(clk_i)
begin
if rising_edge(clk_i) then
if (core_rst = '1' or rx_rst = '1') then
reg_to_mt.rx_stat_bytes_num_i <= (others => '0');
reg_to_mt.rx_stat_frame_ok_i <= '0';
else
if rx_frame_ok_p = '1' then
reg_to_mt.rx_stat_frame_ok_i <= rx_frame_ok_p;
reg_to_mt.rx_stat_bytes_num_i(C_FRAME_BYTES_CNT_LGTH-1 downto 0) <= rx_byte_index - 3;
-- data payload, without FSS, CTRL, CRC, FES
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- extending the rx_fss_received_p until a core_rst or rx_rst is received
p_rx_fss_received_extend : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst = '1' or rx_rst = '1') then
reg_to_mt.rx_stat_pream_ok_i <= '0';
else
if rx_fss_received_p = '1' then
reg_to_mt.rx_stat_pream_ok_i <= '1';
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- extending the rx_crc_wrong_p until a core_rst or rx_rst is received
p_rx_crc_wrong_extend : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst = '1' or rx_rst = '1') then
reg_to_mt.rx_stat_frame_crc_err_i <= '0';
else
if rx_crc_wrong_p = '1' then
reg_to_mt.rx_stat_frame_crc_err_i <= '1';
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter of frames with crc errors since the startup or a core reset (not on every macrocycle)
cmp_rx_crc_err_cnt: incr_counter
generic map(g_counter_lgth => 32)
port map
(clk_i => clk_i,
counter_incr_i => rx_crc_wrong_p,
counter_reinit_i => core_rst,
counter_o => reg_to_mt.rx_stat_crc_err_cnt_i);
---------------------------------------------------------------------------------------------------
-- MASTERFIP TX --
---------------------------------------------------------------------------------------------------
cmp_masterfip_tx: masterfip_tx
port map
(clk_i => clk_i,
rst_i => tx_rst,
speed_i => speed,
tx_bytes_num_i => reg_from_mt.tx_ctrl_bytes_num_o(C_FRAME_BYTES_CNT_LGTH-1 downto 0),
-- num of bytes to serialize; sampled upon tx_start_p
tx_start_p_i => reg_from_mt.tx_ctrl_start_o, -- monostable, 1-clk-tick-long pulse
tx_frame_i => tx_frame,
tx_ctrl_byte_i => reg_from_mt.tx_payld_ctrl_o,
tx_byte_index_o => reg_to_mt.tx_stat_curr_byte_indx_i(C_FRAME_BYTES_CNT_LGTH-1 downto 0),
-- indx of current byte being serialized,
-- counting starts from 0 (indx 0 is
-- the Control byte) up to 262 bytes
tx_end_p_o => tx_completed_p,
tx_d_o => fd_txd,
tx_ena_o => fd_txena,
tx_clk_o => fd_txck);
tx_rst <= core_rst or reg_from_mt.tx_ctrl_rst_o; -- reg_from_mt.tx_ctrl_rst_o is a monostable
fd_txena_o <= fd_txena;
fd_txd_o <= fd_txd;
fd_txck_o <= fd_txck;
reg_to_mt.tx_stat_ena_i <= fd_txena;
---------------------------------------------------------------------------------------------------
-- Signals for the TX --
---------------------------------------------------------------------------------------------------
-- extending the tx_completed_p until a tx_rst or
-- a new request for serialization (reg_from_mt.tx_ctrl_start_o) is received
p_tx_completed_extend : process(clk_i)
begin
if rising_edge(clk_i) then
if(tx_rst = '1' or reg_from_mt.tx_ctrl_start_o = '1') then
reg_to_mt.tx_stat_stop_i <= '0';
else
if tx_completed_p = '1' then
reg_to_mt.tx_stat_stop_i <= '1'; -- stays active until a tx_rst or tx_start_p
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- FielDrive TXER, WDGN, CDN --
---------------------------------------------------------------------------------------------------
-- The following modules provide to the MT information about the status signals coming from the
-- FielDrive: WDGN, CDN, TXER.
---------------------------------------------------------------------------------------------------
-- WDGN: is activated when the FielDrive detects activity > 1024 bytes long;
-- it is kept active until FielDrive's reinitialization with a fd_rstn_o.
-- Note that it is the logic running on the MT that is responsible for activating a fd_rst_o upon
-- the activation of a fd_wdgn.
-- The following processes provide to the MT the filtered fd_wdgn and the macrocycle number when it
-- was activated.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- input synchronizer of the fd_wdgn_a_i signal
cmp_fd_wdgn_sync: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => fd_wdgn_a_i,
synced_o => fd_wdgn);
fd_wdg <= not fd_wdgn;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_fd_wdg_deglitch: gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
dat_i => fd_wdg,
dat_o => reg_to_mt.fd_wdg_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- edge detection
cmp_fd_wdgn_deglitch_p_detect: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => reg_to_mt.fd_wdg_i,
ppulse_o => fd_wdg_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- process that registers the moment within the macrocycle (macrocycle_cnt) when the
-- fd_wdgn_p appeared
p_fd_wdgn_capture : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst = '1' or fd_host_rst = '1') then -- resets upon core reset or FielDrive reset
reg_to_mt.fd_wdg_tstamp_i <= (others => '0');
else
if fd_wdg_p = '1' then
reg_to_mt.fd_wdg_tstamp_i <= '0' & macrocyc_cnt;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- CDN: synch and filtering of the incoming fd_rxcdn_a_i signal.
-- On the processor (MT) side there should be the verification that before a tx_ctrl_start the CDN
-- is inactive.
-- input synchronizer of the fd_rxcdn_a_i signal
cmp_fd_rxcdn_sync: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => fd_rxcdn_a_i,
synced_o => fd_rxcdn);
fd_rxcd <= not fd_rxcdn;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- deglitch filter
cmp_fd_rxcd_deglitch: gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
dat_i => fd_rxcd,
dat_o => reg_to_mt.fd_cd_i);
---------------------------------------------------------------------------------------------------
-- TXER: is activated upon a bus overload/ underload detected by the FielDrive driver outputs;
-- like for example when the WorldFIP cable has been disconnected.
-- It is also activated when during transmission there has been no Manchester-edge detected after
-- the duration of 4 bits.
-- Note that the signal does not need a FielDrive reset to go back to inactive.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- input synchronizer of the fd_txer_a_i signal
cmp_fd_txer_sync: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => fd_txer_a_i,
synced_o => fd_txer);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- deglitch filter
cmp_fd_txer_deglitch: gc_glitch_filt
generic map(g_len => c_DEGLITCH_THRESHOLD)
-- glitches up to c_DEGLITCH_THRESHOLD x c_QUARTZ_PERIOD_NS = 100 ns are ignored;
-- Note that the filter adds a 100 ns delay to the ext_sync signal
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
dat_i => fd_txer,
dat_o => fd_txer_filt);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- edge detection on the fd_txer_filt signal
cmp_fd_txer_deglitch_p_detect: gc_sync_ffs
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => fd_txer_filt,
ppulse_o => fd_txer_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the number of fd_txer_p
cmp_fd_txer_cnt:incr_counter
generic map(g_counter_lgth => 32)
port map
(clk_i => clk_i,
counter_incr_i => fd_txer_p,
counter_reinit_i => fd_txer_cnt_reinit,
counter_is_full_o => open,
counter_o => reg_to_mt.fd_txer_cnt_i);
-- -- -- -- -- -- -- -- -- -- --
fd_txer_cnt_reinit <= '1' when core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rst = '1'
else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- process that registers the moment within the !current! macrocycle (macrocycle_cnt value) when
-- the last fd_txer_p appeared
p_fd_txer_capture : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst = '1' or fd_host_rst = '1' or macrocyc_load_p = '1') then
reg_to_mt.fd_txer_tstamp_i <= (others => '0');
else
if fd_txer_p = '1' then
reg_to_mt.fd_txer_tstamp_i <= '0' & macrocyc_cnt;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- DS18B20U ONE WIRE --
---------------------------------------------------------------------------------------------------
-- Communication with the 1-wire DS18B20U+ for the unique ID and temperature reading;
-- different than in other designs that implement sw-bit-banging, here the communication is
-- implemented in vhdl, so as to simplify the drivers.
-- Note that a temperature reading is provided every second, with the first one a couple of sec
-- after the board power-up/ reset.
cmp_onewire: gc_ds182x_interface
generic map (freq => C_QUARTZ_FREQ_MHZ_INT)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
onewire_b => onewire_b,
id_o => tmp_id,
temper_o => tmp_temper,
id_read_o => onewire_read_p,
pps_p_i => pps_is_zero);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- pps generator based on the 100 MHz clk
cmp_pps_gen: wf_decr_counter
generic map(g_counter_lgth => C_1SEC_CNT_LGTH)
port map
(uclk_i => clk_i,
counter_rst_i => core_rst,
counter_decr_i => '1',
counter_load_i => pps_load_p,
counter_top_i => c_1SEC_CLK_TICKS,
counter_is_zero_o => pps_is_zero);
-- -- -- -- -- -- -- -- -- -- --
pps_load_p <= pps_is_zero; -- looping
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- registering of the read values upon the activation of the id_read_o
p_reg_reading: process(clk_i)
begin
if rising_edge(clk_i) then
if core_rst = '1' then
reg_to_mt.ds1820_temper_i <= (others => '0');
reg_to_mt.ds1820_id_lsb_i <= (others => '0');
reg_to_mt.ds1820_id_msb_i <= (others => '0');
else
if(onewire_read_p = '1') then
reg_to_mt.ds1820_temper_i <= tmp_temper;
reg_to_mt.ds1820_id_lsb_i <= tmp_id (31 downto 0);
reg_to_mt.ds1820_id_msb_i <= tmp_id (63 downto 32);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- LEDs & AUX --
---------------------------------------------------------------------------------------------------
-- active low LEDs
leds_o(0) <= not reg_from_mt.led_rx_act_o;
leds_o(1) <= not reg_from_mt.led_rx_err_o;
leds_o(2) <= not reg_from_mt.led_tx_act_o;
leds_o(3) <= not reg_from_mt.led_tx_err_o;
leds_o(4) <= not reg_from_mt.led_ext_sync_act_o when reg_from_mt.ext_sync_ctrl_oe_n_o = '0' else '0';
leds_o(5) <= not reg_from_mt.led_ext_sync_err_o when reg_from_mt.ext_sync_ctrl_oe_n_o = '0' else '0';
leds_o(7 downto 6) <= "00"; -- not used
leds_o(31 downto 8) <= reg_from_mt.led_dbg_o;
---------------------------------------------------------------------------------------------------
-- Assignments --
---------------------------------------------------------------------------------------------------
-- To simplify the interface between the MT and the fmc_masterfip_core, the serialized/deserialized
-- payload bytes are stored in registers, not in FIFO.
-- The fmc_masterfip_core is copying locally the tx registers upon a tx_stat_start.
-- The processor should copy all the rx data upon a rx_stat_frame_ok; the data stays stable in the
-- rx_frame regs until a rx_rst or until the detection of another rx_stat_frame_ok.
-- This time, in the worst case (bit rate 2.5 Mbps) can be calculated as:
-- (Min Turnaround time of a node = 4 us) + (RP_FIN duration = 19.2 us) = 23.2 us
-- tx regs
tx_frame(0) <= reg_from_mt.tx_payld_reg1_o;
tx_frame(1) <= reg_from_mt.tx_payld_reg2_o;
tx_frame(2) <= reg_from_mt.tx_payld_reg3_o;
tx_frame(3) <= reg_from_mt.tx_payld_reg4_o;
tx_frame(4) <= reg_from_mt.tx_payld_reg5_o;
tx_frame(5) <= reg_from_mt.tx_payld_reg6_o;
tx_frame(6) <= reg_from_mt.tx_payld_reg7_o;
tx_frame(7) <= reg_from_mt.tx_payld_reg8_o;
tx_frame(8) <= reg_from_mt.tx_payld_reg9_o;
tx_frame(9) <= reg_from_mt.tx_payld_reg10_o;
tx_frame(10) <= reg_from_mt.tx_payld_reg11_o;
tx_frame(11) <= reg_from_mt.tx_payld_reg12_o;
tx_frame(12) <= reg_from_mt.tx_payld_reg13_o;
tx_frame(13) <= reg_from_mt.tx_payld_reg14_o;
tx_frame(14) <= reg_from_mt.tx_payld_reg15_o;
tx_frame(15) <= reg_from_mt.tx_payld_reg16_o;
tx_frame(16) <= reg_from_mt.tx_payld_reg17_o;
tx_frame(17) <= reg_from_mt.tx_payld_reg18_o;
tx_frame(18) <= reg_from_mt.tx_payld_reg19_o;
tx_frame(19) <= reg_from_mt.tx_payld_reg20_o;
tx_frame(20) <= reg_from_mt.tx_payld_reg21_o;
tx_frame(21) <= reg_from_mt.tx_payld_reg22_o;
tx_frame(22) <= reg_from_mt.tx_payld_reg23_o;
tx_frame(23) <= reg_from_mt.tx_payld_reg24_o;
tx_frame(24) <= reg_from_mt.tx_payld_reg25_o;
tx_frame(25) <= reg_from_mt.tx_payld_reg26_o;
tx_frame(26) <= reg_from_mt.tx_payld_reg27_o;
tx_frame(27) <= reg_from_mt.tx_payld_reg28_o;
tx_frame(28) <= reg_from_mt.tx_payld_reg29_o;
tx_frame(29) <= reg_from_mt.tx_payld_reg30_o;
tx_frame(30) <= reg_from_mt.tx_payld_reg31_o;
tx_frame(31) <= reg_from_mt.tx_payld_reg32_o;
tx_frame(32) <= reg_from_mt.tx_payld_reg33_o;
tx_frame(33) <= reg_from_mt.tx_payld_reg34_o;
tx_frame(34) <= reg_from_mt.tx_payld_reg35_o;
tx_frame(35) <= reg_from_mt.tx_payld_reg36_o;
tx_frame(36) <= reg_from_mt.tx_payld_reg37_o;
tx_frame(37) <= reg_from_mt.tx_payld_reg38_o;
tx_frame(38) <= reg_from_mt.tx_payld_reg39_o;
tx_frame(39) <= reg_from_mt.tx_payld_reg40_o;
tx_frame(40) <= reg_from_mt.tx_payld_reg41_o;
tx_frame(41) <= reg_from_mt.tx_payld_reg42_o;
tx_frame(42) <= reg_from_mt.tx_payld_reg43_o;
tx_frame(43) <= reg_from_mt.tx_payld_reg44_o;
tx_frame(44) <= reg_from_mt.tx_payld_reg45_o;
tx_frame(45) <= reg_from_mt.tx_payld_reg46_o;
tx_frame(46) <= reg_from_mt.tx_payld_reg47_o;
tx_frame(47) <= reg_from_mt.tx_payld_reg48_o;
tx_frame(48) <= reg_from_mt.tx_payld_reg49_o;
tx_frame(49) <= reg_from_mt.tx_payld_reg50_o;
tx_frame(50) <= reg_from_mt.tx_payld_reg51_o;
tx_frame(51) <= reg_from_mt.tx_payld_reg52_o;
tx_frame(52) <= reg_from_mt.tx_payld_reg53_o;
tx_frame(53) <= reg_from_mt.tx_payld_reg54_o;
tx_frame(54) <= reg_from_mt.tx_payld_reg55_o;
tx_frame(55) <= reg_from_mt.tx_payld_reg56_o;
tx_frame(56) <= reg_from_mt.tx_payld_reg57_o;
tx_frame(57) <= reg_from_mt.tx_payld_reg58_o;
tx_frame(58) <= reg_from_mt.tx_payld_reg59_o;
tx_frame(59) <= reg_from_mt.tx_payld_reg60_o;
tx_frame(60) <= reg_from_mt.tx_payld_reg61_o;
tx_frame(61) <= reg_from_mt.tx_payld_reg62_o;
tx_frame(62) <= reg_from_mt.tx_payld_reg63_o;
tx_frame(63) <= reg_from_mt.tx_payld_reg64_o;
tx_frame(64) <= reg_from_mt.tx_payld_reg65_o;
tx_frame(65) <= reg_from_mt.tx_payld_reg66_o;
tx_frame(66) <= reg_from_mt.tx_payld_reg67_o;
-- rx regs
reg_to_mt.rx_payld_reg1_i <= rx_frame(0);
reg_to_mt.rx_payld_reg2_i <= rx_frame(1);
reg_to_mt.rx_payld_reg3_i <= rx_frame(2);
reg_to_mt.rx_payld_reg4_i <= rx_frame(3);
reg_to_mt.rx_payld_reg5_i <= rx_frame(4);
reg_to_mt.rx_payld_reg6_i <= rx_frame(5);
reg_to_mt.rx_payld_reg7_i <= rx_frame(6);
reg_to_mt.rx_payld_reg8_i <= rx_frame(7);
reg_to_mt.rx_payld_reg9_i <= rx_frame(8);
reg_to_mt.rx_payld_reg10_i <= rx_frame(9);
reg_to_mt.rx_payld_reg11_i <= rx_frame(10);
reg_to_mt.rx_payld_reg12_i <= rx_frame(11);
reg_to_mt.rx_payld_reg13_i <= rx_frame(12);
reg_to_mt.rx_payld_reg14_i <= rx_frame(13);
reg_to_mt.rx_payld_reg15_i <= rx_frame(14);
reg_to_mt.rx_payld_reg16_i <= rx_frame(15);
reg_to_mt.rx_payld_reg17_i <= rx_frame(16);
reg_to_mt.rx_payld_reg18_i <= rx_frame(17);
reg_to_mt.rx_payld_reg19_i <= rx_frame(18);
reg_to_mt.rx_payld_reg20_i <= rx_frame(19);
reg_to_mt.rx_payld_reg21_i <= rx_frame(20);
reg_to_mt.rx_payld_reg22_i <= rx_frame(21);
reg_to_mt.rx_payld_reg23_i <= rx_frame(22);
reg_to_mt.rx_payld_reg24_i <= rx_frame(23);
reg_to_mt.rx_payld_reg25_i <= rx_frame(24);
reg_to_mt.rx_payld_reg26_i <= rx_frame(25);
reg_to_mt.rx_payld_reg27_i <= rx_frame(26);
reg_to_mt.rx_payld_reg28_i <= rx_frame(27);
reg_to_mt.rx_payld_reg29_i <= rx_frame(28);
reg_to_mt.rx_payld_reg30_i <= rx_frame(29);
reg_to_mt.rx_payld_reg31_i <= rx_frame(30);
reg_to_mt.rx_payld_reg32_i <= rx_frame(31);
reg_to_mt.rx_payld_reg33_i <= rx_frame(32);
reg_to_mt.rx_payld_reg34_i <= rx_frame(33);
reg_to_mt.rx_payld_reg35_i <= rx_frame(34);
reg_to_mt.rx_payld_reg36_i <= rx_frame(35);
reg_to_mt.rx_payld_reg37_i <= rx_frame(36);
reg_to_mt.rx_payld_reg38_i <= rx_frame(37);
reg_to_mt.rx_payld_reg39_i <= rx_frame(38);
reg_to_mt.rx_payld_reg40_i <= rx_frame(39);
reg_to_mt.rx_payld_reg41_i <= rx_frame(40);
reg_to_mt.rx_payld_reg42_i <= rx_frame(41);
reg_to_mt.rx_payld_reg43_i <= rx_frame(42);
reg_to_mt.rx_payld_reg44_i <= rx_frame(43);
reg_to_mt.rx_payld_reg45_i <= rx_frame(44);
reg_to_mt.rx_payld_reg46_i <= rx_frame(45);
reg_to_mt.rx_payld_reg47_i <= rx_frame(46);
reg_to_mt.rx_payld_reg48_i <= rx_frame(47);
reg_to_mt.rx_payld_reg49_i <= rx_frame(48);
reg_to_mt.rx_payld_reg50_i <= rx_frame(49);
reg_to_mt.rx_payld_reg51_i <= rx_frame(50);
reg_to_mt.rx_payld_reg52_i <= rx_frame(51);
reg_to_mt.rx_payld_reg53_i <= rx_frame(52);
reg_to_mt.rx_payld_reg54_i <= rx_frame(53);
reg_to_mt.rx_payld_reg55_i <= rx_frame(54);
reg_to_mt.rx_payld_reg56_i <= rx_frame(55);
reg_to_mt.rx_payld_reg57_i <= rx_frame(56);
reg_to_mt.rx_payld_reg58_i <= rx_frame(57);
reg_to_mt.rx_payld_reg59_i <= rx_frame(58);
reg_to_mt.rx_payld_reg60_i <= rx_frame(59);
reg_to_mt.rx_payld_reg61_i <= rx_frame(60);
reg_to_mt.rx_payld_reg62_i <= rx_frame(61);
reg_to_mt.rx_payld_reg63_i <= rx_frame(62);
reg_to_mt.rx_payld_reg64_i <= rx_frame(63);
reg_to_mt.rx_payld_reg65_i <= rx_frame(64);
reg_to_mt.rx_payld_reg66_i <= rx_frame(65);
reg_to_mt.rx_payld_reg67_i <= rx_frame(66);
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
-- chipscope_ila_1 : chipscope_ila
-- port map
-- (CONTROL => CONTROL;
-- CLK => clk_i;
-- TRIG0 => TRIG0;
-- TRIG1 => TRIG1;
-- TRIG2 => TRIG2;
-- TRIG3 => TRIG3);
-- chipscope_icon_1 : chipscope_icon
-- port map ( CONTROL0 => CONTROL);
-- TRIG0(8 downto 0) <= reg_from_mt.tx_ctrl_bytes_num_o;
-- TRIG0(18 downto 11) <= tx_ctrl_byte;
-- TRIG0(27 downto 19) <= reg_to_mt.tx_stat_curr_byte_indx_i;
-- TRIG0(28) <= tx_completed_p;
-- TRIG0(29) <= fd_txena;
-- TRIG0(30) <= fd_txd;
-- TRIG0(31) <= fd_txck;
-- TRIG1 <= tx_frame(0);
-- TRIG1(15 downto 8) <= rx_byte_index;
-- TRIG2(8 downto 0) <= rx_byte_index;
-- TRIG2(9) <= rx_fss_received_p;
-- TRIG2(10) <= rx_byte_ready_p;
-- TRIG2(18 downto 11) <= rx_byte;
-- TRIG2(26 downto 19) <= rx_ctrl_byte;
-- TRIG2(27) <= rx_frame_ok_p;
-- TRIG2(28) <= rx_crc_wrong_p;
-- TRIG2(29) <= core_rst;
-- TRIG2(31 downto 30) <= speed_b1_i & speed_b0_i;
end rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
masterfip-gw-adam-proposed_master/rtl/incr_counter.vhd 0000664 0000000 0000000 00000013370 13422611646 0023576 0 ustar 00root root 0000000 0000000 --_________________________________________________________________________________________________
-- |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- incr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File incr_counter.vhd |
-- Description Increasing counter with synchronous reinitialise and increase enable |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
--=================================================================================================
-- Entity declaration for incr_counter
--=================================================================================================
entity incr_counter is
generic(g_counter_lgth : natural := 32); -- default length
port(
-- INPUTS
clk_i : in std_logic; -- 40 MHz clock
counter_incr_i : in std_logic; -- increment enable
counter_reinit_i : in std_logic; -- reinitializes counter to 0
-- OUTPUT
counter_o : out std_logic_vector (g_counter_lgth-1 downto 0); -- counter
counter_is_full_o : out std_logic); -- counter full indication, when all bits are '1'
end entity incr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Incr_Counter
Incr_Counter: process (clk_i)
begin
if rising_edge (clk_i) then
if counter_reinit_i = '1' then
s_counter <= (others => '0');
elsif counter_incr_i = '1' then
s_counter <= s_counter + 1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= std_logic_vector(s_counter);
counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- masterfip-gw-adam-proposed_master/rtl/masterFIP_pkg.vhd 0000664 0000000 0000000 00000032220 13422611646 0023572 0 ustar 00root root 0000000 0000000 --_________________________________________________________________________________________________
-- |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- masterFIP_pkg |
-- |
---------------------------------------------------------------------------------------------------
-- File masterFIP_pkg.vhd |
-- |
-- Description Definitions of constants, types, entities related to the interface between the |
-- fmc_masterfip_core and the Mock Turtle. |
-- Note that a different package, the wf_package, is used for the WorldFIP specific |
-- constant, types, entities and for the clock constants. |
-- |
-- Author Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wf_package.all; -- WorldFIP specifics package
use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
--=================================================================================================
-- Package declaration for masterFIP_pkg
--=================================================================================================
package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
-- Interface with MT --
-- Array of words with the WorldFIP produced/consumed PAYLOAD bytes --
---------------------------------------------------------------------------------------------------
constant C_BYTE_WIDTH : integer := 8; -- 8-bit bytes
constant C_WORD_WIDTH : integer := 32; -- 32-bit words
-- Declaration of a structure with 67 words of 32-bit each = 268 bytes which represent the max
-- length of a frame, including
-- FSS (2 bytes),
-- CTRL (1 byte),
-- Data (up to 262 for a message),
-- CRC (2 bytes) and
-- FES (1 byte).
-- Note that the deserializer, is registering bytes one by one as they arrive, after the FSS and
-- until the FES detection; therefore the max amount of bytes expected to be counted by the
-- deserializer is 266. Upon the rx_fss_crc_fes_ok_p_o the processor needs to read the rx_ctrl_byte
-- (separate register, not included in the rx_frame structure) and rx_byte_index_o-4 bytes from the
-- rx_frame structure (minus the CTRL, 2x CRC and FES bytes).
-- Note that the serializer, is counting one by one the bytes that are serialized, after the FSS and
-- before the CRC; therefore the max amount of bytes expected to be counted by the serializer is
-- 263.
constant C_MAX_FRAME_WORDS : integer := 67;
constant C_MAX_FRAME_BYTES : integer := 266;
constant C_FRAME_WORDS_CNT_LGTH : integer := 7; -- counter overflows after 128 words = 512 bytes
-- for normal rx operation it should not exceed
-- 67 words; for normal tx operation it should
-- not exceed 66 words
constant C_FRAME_BYTES_CNT_LGTH : integer := 9; -- counter overflows after 128 words = 512 bytes
-- for normal rx operation it should not exceed
-- 266 bytes; for normal tx operation it should
-- not exceed 263 bytes
subtype data_word is std_logic_vector(C_WORD_WIDTH-1 downto 0);
type rx_frame_t is array (C_MAX_FRAME_WORDS-1 downto 0) of data_word;
-- Note that the serializer is not provided with the CRC and FES; the processor needs to provide
-- the CTRL byte (in a separate register, not included in the rx_frame structure) and up to
-- 262 Data bytes. In principle 66 data_words would be sufficient, but for symmetry with rx we kept 67.
type tx_frame_t is array (C_MAX_FRAME_WORDS-1 downto 0) of data_word;
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filters --
---------------------------------------------------------------------------------------------------
-- constant C_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_package
---------------------------------------------------------------------------------------------------
-- Components Declarations: --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component fmc_masterFIP_core is
generic
(g_span : integer := 32;
g_width : integer := 32;
g_simul : boolean := FALSE);
port
(clk_i : in std_logic;
rst_n_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
onewire_b : inout std_logic;
fd_rxcdn_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_n_o : out std_logic;
ext_sync_a_i : in std_logic;
leds_o : out std_logic_vector(g_width-1 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component masterfip_wbgen2_csr is
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_masterfip_in_registers;
regs_o : out t_masterfip_out_registers);
end component;
----------------------------------------------------------------------------------------------------
component masterfip_rx is
port
(clk_i : in std_logic;
speed_i : in std_logic_vector(1 downto 0);
rx_d_a_i : in std_logic;
rst_i : in std_logic;
rx_rst_i : in std_logic;
rx_byte_index_o : out std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
rx_word_index_o : out std_logic_vector(C_FRAME_WORDS_CNT_LGTH-1 downto 0);
rx_ctrl_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0);
rx_ctrl_byte_ok_o : out std_logic;
rx_frame_o : out rx_frame_t;
rx_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0);
rx_byte_ready_p_o : out std_logic;
rx_fss_crc_fes_ok_p_o : out std_logic;
rx_fss_received_p_o : out std_logic;
rx_crc_wrong_p_o : out std_logic;
rx_bytes_num_err_o : out std_logic);
end component masterfip_rx;
---------------------------------------------------------------------------------------------------
component masterfip_tx is
port
(clk_i : in std_logic;
speed_i : in std_logic_vector(1 downto 0);
rst_i : in std_logic;
tx_start_p_i : in std_logic;
tx_bytes_num_i : in std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
tx_frame_i : in tx_frame_t;
tx_ctrl_byte_i : in std_logic_vector(C_BYTE_WIDTH-1 downto 0);
tx_byte_index_o : out std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
tx_end_p_o : out std_logic;
tx_d_o : out std_logic;
tx_ena_o : out std_logic;
tx_clk_o : out std_logic);
end component masterfip_tx;
---------------------------------------------------------------------------------------------------
component decr_counter
generic
(width : integer := 32);
port
(clk_i : in std_logic;
rst_i : in std_logic;
counter_load_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0);
counter_is_zero_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0));
end component;
---------------------------------------------------------------------------------------------------
component incr_counter is
generic
(g_counter_lgth : natural := 4);
port
(clk_i : in std_logic;
counter_incr_i : in std_logic;
counter_reinit_i : in std_logic;
counter_o : out std_logic_vector(g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic);
end component incr_counter;
--=================================================================================================
-- package end
--=================================================================================================
end masterFIP_pkg;
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- masterfip-gw-adam-proposed_master/rtl/masterfip_rx.vhd 0000664 0000000 0000000 00000056244 13422611646 0023616 0 ustar 00root root 0000000 0000000 --_________________________________________________________________________________________________
-- |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- masterfip_rx |
-- |
---------------------------------------------------------------------------------------------------
-- File masterfip_rx.vhd |
-- |
-- Description The unit groups the main actions that regard FIELDRIVE data reception. |
-- Figure 1 shows the main units/processes; the units RX DESERIALIZER, RX OSC and |
-- RX DEGLITCHER come unmodified from the nanoFIP project. |
-- Figure 2 shows the WorldFIP frame structure; note that the fmc_masterfip_core |
-- ignores completely the notion of PDU_TYPE, LGTH, MPS, etc fields inside the |
-- PAYLOAD part of the frame and is not checking them at reception. |
-- It is the processor (MT) that is handling individually the bytes inside the |
-- PAYLOAD frame field. On the other hand the FSS, CRC and FES fields are checked |
-- and validated by the masterfip_rx. |
-- As long as the rx_rst_i is not activated the deserializer probes the bus |
-- looking for a FSS; after the FSS detection, the deserialized bytes are packed |
-- one-by-one in 32-bit words to be provided to the MT. Upon the detection of a FES |
-- either the rx_fss_crc_fes_ok_p_o or the rx_crc_wrong_p_o is activated to signal to|
-- MT for the end of a correct or erroneous frame. |
-- |
-- RX OSC for the clock recovery |
-- |
-- RX for the filtering of the input FD_RXD |
-- |
-- RX DESERIALIZER for the bytes retrieval; also detects FSS/FES & checks CRC |
-- |
-- BYTES_C for the counting of the retrieved bytes |
-- |
-- CREATE 32bit WORDS for the formation of 32-bit words to be provided to the |
-- processor (Mock Turtle for example) |
-- |
-- Mock Turtle |
-- ___________________________________________________________ |
-- | | |
-- | _________ _______________________ | |
-- | | | | | | |
-- | | BYTES_C | | CREATE 32bit WORDS | | |
-- | |_________| |_______________________| | |
-- | /\ /\ _________ | |
-- | _______________________________________ | | | |
-- | | | | | | |
-- | | RX DESERIALIZER | | RX OSC | | |
-- | | | < | | | |
-- | |_______________________________________| | | | |
-- | /\ |_________| | |
-- | _______________________________________ | |
-- | | | | |
-- | | RX DEGLITCHER | | |
-- | |_______________________________________| | |
-- | | |
-- |___________________________________________________________| |
-- /\ |
-- ___________________________________________________________________ |
-- 0_____________________________FIELDBUS______________________________0 |
-- |
-- ___________ ______ ________________________________________ ___________ _______ |
-- |____FSS____|_CTRL_||_____________..DATA/PAYLOAD..___________||____CRC____|__FES__| |
-- |
-- Figure 2: WorldFIP Frame structure |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use IEEE.math_real.all;
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.wf_package.all;
--=================================================================================================
-- Entity declaration for masterfip_rx
--=================================================================================================
entity masterfip_rx is port(
-- INPUTS
clk_i : in std_logic; -- only one clk domain
rst_i : in std_logic; -- core rst, synched with clk_i
rx_rst_i : in std_logic; -- dedicated rx reset during transmission OR
-- reset pulse from the processor when for eg. a
-- frame is rejected during reception
-- (ex: RP_DAT > 133 bytes, wrong CTRL byte)
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
rx_d_a_i : in std_logic; -- FielDrive receiver data
-- OUTPUTS
rx_byte_ready_p_o : out std_logic; -- pulse indicating a new retrieved byte
rx_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0);
-- currently retrieved byte
rx_byte_index_o : out std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
-- index of currently retrieved byte
-- counting starts after FSS; it includes
-- the CTRL, DATA, CRC and FES fields;
-- counting starts from 0 and normally
-- the value should not exceed 265
rx_word_index_o : out std_logic_vector(C_FRAME_WORDS_CNT_LGTH-1 downto 0);
-- index of currently retrieved word
-- counting starts from 0 and normally
-- the value should not exceed 66
rx_ctrl_byte_o : out std_logic_vector(C_BYTE_WIDTH-1 downto 0); -- frame CTRL byte
rx_ctrl_byte_ok_o : out std_logic; -- active after the reception of the CTRL byte (first
-- byte after FSS) and until a rst_i OR rst_rx_i
rx_frame_o : out rx_frame_t; -- frame DATA bytes
-- structure with 67 words of 32-bit each = 268 bytes
-- able to house a frame of max length.
-- Upon the rx_fss_crc_fes_ok_p_o the processor needs
-- to read the rx_ctrl_byte and rx_byte_index_o - 4
-- bytes from the rx_frame_o. The content of rx_frame_o
-- changes upon the end of reception of a new frame
-- (i.e. a new rx_fss_crc_fes_ok_p_o).
rx_fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame with correct FSS, FES & CRC;
-- pulse upon FES detection
rx_crc_wrong_p_o : out std_logic; -- indication of a frame with wrong CRC; pulse upon FES
rx_fss_received_p_o : out std_logic; -- pulse upon FSS detection (ID/ RP_DAT)
rx_bytes_num_err_o : out std_logic); -- active after the reception of > C_MAX_FRAME_BYTES bytes
-- and until a rst_i OR rst_rx_i
end entity masterfip_rx;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture struc of masterfip_rx is
-- wf_rx_osc
signal rx_osc_rst, adjac_bits_window : std_logic;
signal signif_edge_window : std_logic;
signal sample_bit_p : std_logic;
signal sample_manch_bit_p : std_logic;
-- wf_rx_deglitcher
signal fd_rxd_filt, rxd_filt_edge_p : std_logic;
signal fd_rxd_filt_f_edge_p : std_logic;
signal fd_rxd_filt_r_edge_p : std_logic;
-- wf_rx_deserializer
signal rx_byte_ready_p : std_logic;
signal rx_fss_crc_fes_ok_p : std_logic;
signal rx_byte : std_logic_vector (C_BYTE_WIDTH-1 downto 0);
-- retrieved bytes into 32-bit regs
signal byte0, byte1, byte2, byte3 : std_logic_vector(C_BYTE_WIDTH-1 downto 0);
signal zero : std_logic_vector(C_BYTE_WIDTH-1 downto 0) := (others => '0');
signal word32_num : integer range 0 to C_MAX_FRAME_WORDS-1;
-- bytes counter
signal rx_byte_index, rx_byte_index_d1 : std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
signal bytes_c_rst : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Deserializer as in the nanoFIP project --
---------------------------------------------------------------------------------------------------
cmp_rx_deglitcher: wf_rx_deglitcher
port map(
uclk_i => clk_i,
nfip_rst_i => rx_rst_i,
fd_rxd_a_i => rx_d_a_i,
-----------------------------------------------------------------
fd_rxd_filt_o => fd_rxd_filt,
fd_rxd_filt_edge_p_o => rxd_filt_edge_p,
fd_rxd_filt_f_edge_p_o => fd_rxd_filt_f_edge_p);
-----------------------------------------------------------------
fd_rxd_filt_r_edge_p <= rxd_filt_edge_p and (not fd_rxd_filt_f_edge_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_deserializer: wf_rx_deserializer
port map(
uclk_i => clk_i,
nfip_rst_i => rst_i,
rx_rst_i => rx_rst_i,
fd_rxd_f_edge_p_i => fd_rxd_filt_f_edge_p,
fd_rxd_r_edge_p_i => fd_rxd_filt_r_edge_p,
fd_rxd_i => fd_rxd_filt,
sample_bit_p_i => sample_bit_p,
sample_manch_bit_p_i => sample_manch_bit_p,
signif_edge_window_i => signif_edge_window,
adjac_bits_window_i => adjac_bits_window,
-----------------------------------------------------------------
byte_o => rx_byte,
byte_ready_p_o => rx_byte_ready_p,
fss_crc_fes_ok_p_o => rx_fss_crc_fes_ok_p,
rx_osc_rst_o => rx_osc_rst,
fss_received_p_o => rx_fss_received_p_o,
crc_wrong_p_o => rx_crc_wrong_p_o);
-----------------------------------------------------------------
rx_byte_ready_p_o <= rx_byte_ready_p;
rx_byte_o <= rx_byte;
rx_fss_crc_fes_ok_p_o <= rx_fss_crc_fes_ok_p;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_osc: wf_rx_osc
port map(
uclk_i => clk_i,
rate_i => speed_i,
nfip_rst_i => rst_i,
fd_rxd_edge_p_i => rxd_filt_edge_p,
rx_osc_rst_i => rx_osc_rst,
-----------------------------------------------------------------
rx_manch_clk_p_o => sample_manch_bit_p,
rx_bit_clk_p_o => sample_bit_p,
rx_signif_edge_window_o => signif_edge_window,
rx_adjac_bits_window_o => adjac_bits_window);
-----------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- bytes counter --
---------------------------------------------------------------------------------------------------
cmp_rx_bytes_cnt: incr_counter
generic map(g_counter_lgth => C_FRAME_BYTES_CNT_LGTH)
port map(
clk_i => clk_i,
counter_reinit_i => bytes_c_rst,
counter_incr_i => rx_byte_ready_p,
counter_is_full_o => open,
-------------------------------------------------------
counter_o => rx_byte_index);
-------------------------------------------------------
bytes_c_rst <= rst_i or rx_rst_i;
rx_byte_index_o <= rx_byte_index;
---------------------------------------------------------------------------------------------------
-- rx bytes exceeded C_MAX_FRAME_BYTES --
---------------------------------------------------------------------------------------------------
-- indication that the rx counter exceeded the max expected number of bytes
p_rx_bytes_num_err: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
rx_bytes_num_err_o <= '0';
else
if unsigned(rx_byte_index) > C_MAX_FRAME_BYTES then
rx_bytes_num_err_o <= '1';
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- combination of four retrieved bytes to a 32-bit word --
---------------------------------------------------------------------------------------------------
-- note: the values of the CTRL byte and all payload regs are kept till a rx_rst_i or a rst_i
p_create_32bit_words: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
byte0 <= (others => '0');
byte1 <= (others => '0');
byte2 <= (others => '0');
byte3 <= (others => '0');
rx_ctrl_byte_o <= (others => '0');
rx_ctrl_byte_ok_o <= '0';
else
if rx_byte_ready_p = '1' then
if unsigned(rx_byte_index) = resize(unsigned(c_CTRL_BYTE_INDEX),C_FRAME_BYTES_CNT_LGTH) then
rx_ctrl_byte_o <= rx_byte; -- CTRL byte stored in separate word from the rest of the frame
rx_ctrl_byte_ok_o <= '1'; -- value kept till a rst
else
byte0 <= rx_byte;
byte1 <= byte0;
byte2 <= byte1;
byte3 <= byte2;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Storage of consumed bytes to the cons_frame regs --
---------------------------------------------------------------------------------------------------
-- transfer 32bit words to the cons_frame registers
p_delay: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
rx_byte_index_d1 <= (others =>'0'); -- needed for synching
else
if rx_byte_ready_p = '1' then
rx_byte_index_d1 <= rx_byte_index;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
p_data_transfer_to_regs: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
word32_num <= 0;
rx_frame_o <= (others =>(others =>'0'));
else
-- upon rx_fss_crc_fes_ok_p, the last 32bit word will contain for sure CRC0 and CRC1
-- and it may also contain one or two bytes of data.
-- the last word will always include as last bytes, byte1 and byte0: the two CRC bytes.
-- it could also include one or two useful data bytes
if rx_fss_crc_fes_ok_p = '1' then
if word32_num = 0 then -- only in the case of RP_FIN, where there are not enough
-- bytes to create a word; needed for keeping the MT sw generic
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
elsif (unsigned(rx_byte_index)-2) mod 4 = 3 then -- [CRC|CRC|BYTE|BYTE]
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; -- byte 3 and byte 2 are useful
elsif (unsigned(rx_byte_index)-2) mod 4 = 2 then -- [0|CRC|CRC|BYTE]
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= zero & byte0 & byte1 & byte2; -- one useful data byte: byte2 last byte
end if; -- Note: for [CRC|BYTE|BYTE|BYTE], upon
-- rx_fss_crc_fes_ok_p a new word has been created
-- for the rest of the bytes, i.e. everything before the rx_fss_crc_fes_ok_p, a new word is
-- created after the reception of 4 bytes.
-- note that rx_byte_index is checked to be within the limits [1..262], as:
-- rx_byte_index = 0 refers to the CTRL byte that is written in a separate word, and
-- when rx_byte_index = 262: the one-but-last word (rx_frame_o(66)) of a max-length-frame
-- is written; the last word (rx_frame_o(67)) of a max-length-frame will be written
-- upon rx_fss_crc_fes_ok_p.
elsif (rx_byte_ready_p = '1' and unsigned(rx_byte_index_d1) > 0 and unsigned(rx_byte_index_d1) < 263 and unsigned(rx_byte_index_d1) mod 4 = 0) then
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rx_word_index_o <= std_logic_vector(to_unsigned(word32_num,C_FRAME_WORDS_CNT_LGTH));
end architecture struc;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- masterfip-gw-adam-proposed_master/rtl/masterfip_tx.vhd 0000664 0000000 0000000 00000047735 13422611646 0023625 0 ustar 00root root 0000000 0000000 --_________________________________________________________________________________________________
-- |
-- |masterFIP core| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- masterfip_tx |
-- |
---------------------------------------------------------------------------------------------------
-- File masterfip_tx.vhd |
-- |
-- Description The unit groups the main actions that regard FIELDRIVE data transmission. |
-- Figure 1 shows the main units/processes; the units TX SERIALIZER and TX OSC come |
-- unmodified from the nanoFIP project. |
-- Figure 2 shows the frame structure; note that the fmc_masterfip_core ignores |
-- completely the notion of PDU_TYPE, LGTH, MPS, etc fields inside the PAYLOAD |
-- part of the frame. It is the processor (MT) that is providing all the bytes inside|
-- the PAYLOAD frame field. On the other hand the FSS, CRC and FES fields are |
-- generated by the masterfip_tx. |
-- The serialization starts upon a rising edge on the tx_start_p_i and upon the end |
-- of the FES transmission the masterfip_tx activates the tx_end_p_o signal. |
-- |
-- o TX SERIALIZER this unit comes unmodified from the nanoFIP project. |
-- It receives bytes from the processor trough the |
-- tx_frame structure, encodes them in Manchester 2, adds the FSS, |
-- CRC, FES fields and puts one by one bits to the FIELDRIVE |
-- output FD_TXD following the synchronization signals from the |
-- wf_tx_osc unit. It also generates the output FD_TXENA. |
-- |
-- o TX OSC this unit comes unmodified from the nanoFIP project. |
-- It generates the output FD_TXCK as well as an array of pulses, |
-- tx_sched_p_buff, used for the synchronization of the |
-- TX SERIALIZER's actions. |
-- |
-- o DATA RETRIEVAL this unit copies the bytes provided by the processor upon |
-- the activation of the signal tx_start. |
-- |
-- Mock Turtle |
-- ___________________________________________________________ |
-- | _______________________________ | |
-- | | | | |
-- | | DATA RETRIEVAL | | |
-- | |_______________________________| | |
-- | \/ \/ | |
-- | _________ _______________ | |
-- | | | | | | |
-- | | BYTES_C | | SELECT BYTE | | |
-- | |_________| |_______________| | |
-- | \/ | |
-- | _____________ __________________________________ | |
-- | | | | | | |
-- | | TX OSC | > | TX SERIALIZER | | |
-- | | | | | | |
-- | |_____________| |__________________________________| | |
-- |___________________________________________________________| |
-- \/ |
-- ___________________________________________________________________ |
-- 0_____________________________FIELDBUS______________________________O |
-- |
-- Figure 1: Module architecture |
-- |
-- ___________ ______ ________________________________________ ___________ _______ |
-- |____FSS____|_CTRL_||_____________..DATA/PAYLOAD..___________||____CRC____|__FES__| |
-- |
-- Figure 2: WorldFIP Frame structure |
-- |
-- Authors Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.masterFIP_pkg.all; -- definitions of types, constants, entities
use work.wf_package.all;
--=================================================================================================
-- Entity declaration for masterfip_tx
--=================================================================================================
entity masterfip_tx is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_simul : boolean := FALSE); -- set to TRUE when instantiated in a test-bench
port(
-- INPUTS
clk_i : in std_logic; -- only one clk domain
rst_i : in std_logic; -- core rst, synched with clk_i
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
tx_frame_i : in tx_frame_t; -- frame PAYLOAD bytes;
-- structure with 67 words of 32-bit each,
-- able to house a frame of max length;
-- upon tx_start_p_i, tx_bytes_num_i are
-- copied locally to be serialized
tx_bytes_num_i : in std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
-- number of bytes to be serialized
tx_ctrl_byte_i : in std_logic_vector(C_BYTE_WIDTH-1 downto 0);
-- frame CTRL byte
tx_start_p_i : in std_logic; -- indication for the start of the serialization
-- OUTPUTS
tx_byte_index_o : out std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
-- indx of byte currently being serialized (0-262)
tx_end_p_o : out std_logic; -- 1-clk-tick long pulse upon termination of
-- transmission (after FES)
tx_d_o : out std_logic; -- FIELDRIVE transmitter data
tx_ena_o : out std_logic; -- FIELDRIVE transmitter enable
tx_clk_o : out std_logic); -- FIELDRIVE transmitter line driver half bit clk
end entity masterfip_tx;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture struc of masterfip_tx is
-- frame bytes
signal prod_bytes_c : std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
signal zero : unsigned(C_FRAME_BYTES_CNT_LGTH-1 downto 0) := (others => '0');
signal ctrl_byte, tx_byte : std_logic_vector(C_BYTE_WIDTH-1 downto 0);
signal prod_frame : tx_frame_t;
signal word32_num : integer range 0 to C_MAX_FRAME_WORDS-1;
signal word32 : std_logic_vector(C_WORD_WIDTH-1 downto 0);
-- bytes counter
signal bytes_num : std_logic_vector(C_FRAME_BYTES_CNT_LGTH-1 downto 0);
signal prod_data_lgth_match : std_logic;
signal last_data_byte_p, last_data_byte_p_d : std_logic;
-- signals for wf_tx_osc
signal s_tx_clk_p_buff : std_logic_vector(c_TX_SCHED_BUFF_LGTH-1 downto 0);
signal s_tx_osc_rst_p : std_logic;
-- signals for wf_tx_serializer
signal byte_request_accept_p : std_logic;
signal byte_request_accept_p_d1 : std_logic;
signal byte_request_accept_p_d2 : std_logic;
signal tx_byte_request_p : std_logic;
signal last_data_byte_p_tmp : std_logic;
signal byte_request_accept_p_tmp : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Copy of the frame data --
---------------------------------------------------------------------------------------------------
-- Local copy of the data bytes upon the tx_start_p_i.
-- All the frame bytes are copied to local registers; like this the frame data remain stable
-- until the next tx_start_p_i arrives.
p_data_retrieval: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
prod_frame <= ((others => (others => '0')));
ctrl_byte <= (others => '0');
bytes_num <= (others => '0');
else
if tx_start_p_i = '1' then
prod_frame <= tx_frame_i; -- copying of the DATA bytes
ctrl_byte <= tx_ctrl_byte_i; -- copying of the CTRL byte
bytes_num <= tx_bytes_num_i; -- num of bytes to serialize from the prod_frame
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Sequential byte selection --
---------------------------------------------------------------------------------------------------
-- The following processes are responsible for the selection of the next byte to be serialised.
-- Following the frame structure of Figure 2, after the FSS (which is hard-coded in the
-- wf_tx_serializer's state machine), the first byte to serialize is the CTRL byte that comes from
-- the dedicated register ctrl_byte. Then, bytes are selected one by one from the prod_frame words
-- array, starting from byte(0) of the prod_frame(0). The wf_tx_serializer's signal
-- tx_byte_request_p indicates the need to retrieve a new byte for serialization.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Selection of one 32-bit word of the prod_frame words array
p_select_word: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
word32_num <= 0;
else
if (unsigned(prod_bytes_c)) mod 4 = 0 and tx_byte_request_p = '1' and unsigned(prod_bytes_c) > 0 then
word32_num <= word32_num + 1;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of an incr_counter for the counting of the number of the bytes that are
-- being serialized.
cmp_tx_bytes_cnt: incr_counter
generic map(g_counter_lgth => C_FRAME_BYTES_CNT_LGTH)
port map(
clk_i => clk_i,
counter_reinit_i => tx_start_p_i,
counter_incr_i => tx_byte_request_p,
-------------------------------------------------------
counter_o => prod_bytes_c);
-------------------------------------------------------
tx_byte_index_o <= prod_bytes_c;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Selection of one byte
word32 <= prod_frame(word32_num);
tx_byte <= ctrl_byte when unsigned(prod_bytes_c) = zero else -- first byte to serialize is the CTRL
word32(7 downto 0) when unsigned(prod_bytes_c) mod 4 = 1 else -- byte(0) (lsb) of a prod_frame word
word32(15 downto 8) when unsigned(prod_bytes_c) mod 4 = 2 else -- byte(1) of a prod_frame word
word32(23 downto 16) when unsigned(prod_bytes_c) mod 4 = 3 else -- byte(2) of a prod_frame word
word32(31 downto 24); -- byte(3) (msb) of a prod_frame word
---------------------------------------------------------------------------------------------------
-- TX as in the nanoFIP project --
---------------------------------------------------------------------------------------------------
cmp_tx_serializer: wf_tx_serializer
port map(
uclk_i => clk_i,
nfip_rst_i => rst_i,
tx_start_p_i => tx_start_p_i,
byte_i => tx_byte,
byte_request_accept_p_i => byte_request_accept_p,
last_byte_p_i => last_data_byte_p,
tx_sched_p_buff_i => s_tx_clk_p_buff,
-----------------------------------------------
tx_byte_request_p_o => tx_byte_request_p,
tx_completed_p_o => tx_end_p_o,
tx_data_o => tx_d_o,
tx_osc_rst_p_o => s_tx_osc_rst_p,
tx_enable_o => tx_ena_o);
-----------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tx_osc: wf_tx_osc
port map(
uclk_i => clk_i,
rate_i => speed_i,
nfip_rst_i => rst_i,
tx_osc_rst_p_i => s_tx_osc_rst_p,
-----------------------------------------------
tx_clk_o => tx_clk_o,
tx_sched_p_buff_o => s_tx_clk_p_buff);
-----------------------------------------------
---------------------------------------------------------------------------------------------------
-- Signals essential to the serializer --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- when s_prod_data_lgth bytes have been counted, the signal prod_data_lgth_match is activated
prod_data_lgth_match <= '1' when prod_bytes_c = bytes_num else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
p_delay: process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
last_data_byte_p <= '0'; -- indication of the last DATA byte (CRC, FES not included)
last_data_byte_p_d <= '0';
byte_request_accept_p_d1 <= '0';
byte_request_accept_p_d2 <= '0';
else
last_data_byte_p_d <= last_data_byte_p_tmp;
last_data_byte_p <= last_data_byte_p_d;
byte_request_accept_p_d1 <= byte_request_accept_p_tmp;
byte_request_accept_p_d2 <= byte_request_accept_p_d1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
byte_request_accept_p_tmp <= tx_byte_request_p or tx_start_p_i;
last_data_byte_p_tmp <= prod_data_lgth_match and tx_byte_request_p;
byte_request_accept_p <= byte_request_accept_p_d2; -- response to wf_tx_serializer's request
-- for a byte
end architecture struc;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
--------------------------------------------------------------------------------------------------- masterfip-gw-adam-proposed_master/rtl/masterfip_wbgen2_csr.vhd 0000664 0000000 0000000 00000237437 13422611646 0025225 0 ustar 00root root 0000000 0000000 ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC masterFIP core registers
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 07/17/17 17:07:34
-- Version : 0x00020000
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.masterfip_wbgen2_pkg.all;
entity masterfip_wbgen2_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
regs_i : in t_masterfip_in_registers;
regs_o : out t_masterfip_out_registers
);
end masterfip_wbgen2_csr;
architecture syn of masterfip_wbgen2_csr is
signal masterfip_ver_id_int : std_logic_vector(31 downto 0);
signal masterfip_rst_core_dly0 : std_logic ;
signal masterfip_rst_core_int : std_logic ;
signal masterfip_rst_fd_dly0 : std_logic ;
signal masterfip_rst_fd_int : std_logic ;
signal masterfip_led_rx_act_int : std_logic ;
signal masterfip_led_rx_err_int : std_logic ;
signal masterfip_led_tx_act_int : std_logic ;
signal masterfip_led_tx_err_int : std_logic ;
signal masterfip_led_ext_sync_act_int : std_logic ;
signal masterfip_led_ext_sync_err_int : std_logic ;
signal masterfip_led_dbg_int : std_logic_vector(23 downto 0);
signal masterfip_ext_sync_ctrl_term_en_int : std_logic ;
signal masterfip_ext_sync_ctrl_dir_int : std_logic ;
signal masterfip_ext_sync_ctrl_oe_n_int : std_logic ;
signal masterfip_ext_sync_ctrl_p_cnt_rst_int : std_logic ;
signal masterfip_ext_sync_ctrl_opt_int : std_logic ;
signal masterfip_ext_sync_ctrl_safe_wind_int : std_logic ;
signal masterfip_macrocyc_lgth_int : std_logic_vector(30 downto 0);
signal masterfip_macrocyc_start_dly0 : std_logic ;
signal masterfip_macrocyc_start_int : std_logic ;
signal masterfip_turnar_lgth_int : std_logic_vector(30 downto 0);
signal masterfip_turnar_start_dly0 : std_logic ;
signal masterfip_turnar_start_int : std_logic ;
signal masterfip_silen_lgth_int : std_logic_vector(30 downto 0);
signal masterfip_silen_start_dly0 : std_logic ;
signal masterfip_silen_start_int : std_logic ;
signal masterfip_tx_ctrl_rst_dly0 : std_logic ;
signal masterfip_tx_ctrl_rst_int : std_logic ;
signal masterfip_tx_ctrl_start_dly0 : std_logic ;
signal masterfip_tx_ctrl_start_int : std_logic ;
signal masterfip_tx_ctrl_bytes_num_int : std_logic_vector(15 downto 0);
signal masterfip_rx_ctrl_rst_dly0 : std_logic ;
signal masterfip_rx_ctrl_rst_int : std_logic ;
signal masterfip_tx_payld_ctrl_int : std_logic_vector(7 downto 0);
signal masterfip_tx_payld_reg1_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg2_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg3_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg4_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg5_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg6_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg7_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg8_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg9_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg10_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg11_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg12_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg13_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg14_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg15_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg16_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg17_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg18_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg19_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg20_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg21_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg22_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg23_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg24_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg25_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg26_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg27_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg28_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg29_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg30_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg31_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg32_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg33_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg34_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg35_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg36_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg37_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg38_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg39_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg40_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg41_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg42_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg43_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg44_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg45_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg46_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg47_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg48_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg49_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg50_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg51_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg52_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg53_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg54_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg55_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg56_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg57_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg58_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg59_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg60_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg61_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg62_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg63_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg64_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg65_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg66_int : std_logic_vector(31 downto 0);
signal masterfip_tx_payld_reg67_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal rwaddr_reg : std_logic_vector(7 downto 0);
signal ack_in_progress : std_logic ;
begin
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
masterfip_ver_id_int <= "00000000000000100000000000000000";
masterfip_rst_core_int <= '0';
masterfip_rst_fd_int <= '0';
masterfip_led_rx_act_int <= '0';
masterfip_led_rx_err_int <= '0';
masterfip_led_tx_act_int <= '0';
masterfip_led_tx_err_int <= '0';
masterfip_led_ext_sync_act_int <= '0';
masterfip_led_ext_sync_err_int <= '0';
masterfip_led_dbg_int <= "000000000000000000000000";
masterfip_ext_sync_ctrl_term_en_int <= '0';
masterfip_ext_sync_ctrl_dir_int <= '0';
masterfip_ext_sync_ctrl_oe_n_int <= '0';
masterfip_ext_sync_ctrl_p_cnt_rst_int <= '0';
masterfip_ext_sync_ctrl_opt_int <= '0';
masterfip_ext_sync_ctrl_safe_wind_int <= '0';
masterfip_macrocyc_lgth_int <= "0000000000000000000000000000000";
masterfip_macrocyc_start_int <= '0';
masterfip_turnar_lgth_int <= "0000000000000000000000000000000";
masterfip_turnar_start_int <= '0';
masterfip_silen_lgth_int <= "0000000000000000000000000000000";
masterfip_silen_start_int <= '0';
masterfip_tx_ctrl_rst_int <= '0';
masterfip_tx_ctrl_start_int <= '0';
masterfip_tx_ctrl_bytes_num_int <= "0000000000000000";
masterfip_rx_ctrl_rst_int <= '0';
masterfip_tx_payld_ctrl_int <= "00000000";
masterfip_tx_payld_reg1_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg2_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg3_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg4_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg5_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg6_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg7_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg8_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg9_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg10_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg11_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg12_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg13_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg14_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg15_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg16_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg17_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg18_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg19_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg20_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg21_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg22_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg23_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg24_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg25_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg26_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg27_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg28_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg29_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg30_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg31_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg32_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg33_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg34_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg35_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg36_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg37_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg38_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg39_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg40_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg41_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg42_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg43_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg44_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg45_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg46_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg47_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg48_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg49_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg50_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg51_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg52_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg53_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg54_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg55_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg56_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg57_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg58_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg59_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg60_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg61_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg62_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg63_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg64_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg65_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg66_int <= "00000000000000000000000000000000";
masterfip_tx_payld_reg67_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
masterfip_rst_core_int <= '0';
masterfip_rst_fd_int <= '0';
masterfip_macrocyc_start_int <= '0';
masterfip_turnar_start_int <= '0';
masterfip_silen_start_int <= '0';
masterfip_tx_ctrl_rst_int <= '0';
masterfip_tx_ctrl_start_int <= '0';
masterfip_rx_ctrl_rst_int <= '0';
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(7 downto 0) is
when "00000000" =>
if (wb_we_i = '1') then
masterfip_ver_id_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_ver_id_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000001" =>
if (wb_we_i = '1') then
masterfip_rst_core_int <= wrdata_reg(0);
masterfip_rst_fd_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00000010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= "11000000000000001111111111101110";
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000011" =>
if (wb_we_i = '1') then
masterfip_led_rx_act_int <= wrdata_reg(0);
masterfip_led_rx_err_int <= wrdata_reg(1);
masterfip_led_tx_act_int <= wrdata_reg(2);
masterfip_led_tx_err_int <= wrdata_reg(3);
masterfip_led_ext_sync_act_int <= wrdata_reg(4);
masterfip_led_ext_sync_err_int <= wrdata_reg(5);
masterfip_led_dbg_int <= wrdata_reg(31 downto 8);
end if;
rddata_reg(0) <= masterfip_led_rx_act_int;
rddata_reg(1) <= masterfip_led_rx_err_int;
rddata_reg(2) <= masterfip_led_tx_act_int;
rddata_reg(3) <= masterfip_led_tx_err_int;
rddata_reg(4) <= masterfip_led_ext_sync_act_int;
rddata_reg(5) <= masterfip_led_ext_sync_err_int;
rddata_reg(31 downto 8) <= masterfip_led_dbg_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= regs_i.ds1820_temper_i;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.ds1820_id_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.ds1820_id_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000111" =>
if (wb_we_i = '1') then
masterfip_ext_sync_ctrl_term_en_int <= wrdata_reg(0);
masterfip_ext_sync_ctrl_dir_int <= wrdata_reg(1);
masterfip_ext_sync_ctrl_oe_n_int <= wrdata_reg(2);
masterfip_ext_sync_ctrl_p_cnt_rst_int <= wrdata_reg(8);
masterfip_ext_sync_ctrl_opt_int <= wrdata_reg(16);
masterfip_ext_sync_ctrl_safe_wind_int <= wrdata_reg(24);
end if;
rddata_reg(0) <= masterfip_ext_sync_ctrl_term_en_int;
rddata_reg(1) <= masterfip_ext_sync_ctrl_dir_int;
rddata_reg(2) <= masterfip_ext_sync_ctrl_oe_n_int;
rddata_reg(8) <= masterfip_ext_sync_ctrl_p_cnt_rst_int;
rddata_reg(16) <= masterfip_ext_sync_ctrl_opt_int;
rddata_reg(24) <= masterfip_ext_sync_ctrl_safe_wind_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.ext_sync_p_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(1 downto 0) <= regs_i.speed_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001010" =>
if (wb_we_i = '1') then
masterfip_macrocyc_lgth_int <= wrdata_reg(30 downto 0);
masterfip_macrocyc_start_int <= wrdata_reg(31);
end if;
rddata_reg(30 downto 0) <= masterfip_macrocyc_lgth_int;
rddata_reg(31) <= '0';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= regs_i.macrocyc_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.macrocyc_num_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001101" =>
if (wb_we_i = '1') then
masterfip_turnar_lgth_int <= wrdata_reg(30 downto 0);
masterfip_turnar_start_int <= wrdata_reg(31);
end if;
rddata_reg(30 downto 0) <= masterfip_turnar_lgth_int;
rddata_reg(31) <= '0';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= regs_i.turnar_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001111" =>
if (wb_we_i = '1') then
masterfip_silen_lgth_int <= wrdata_reg(30 downto 0);
masterfip_silen_start_int <= wrdata_reg(31);
end if;
rddata_reg(30 downto 0) <= masterfip_silen_lgth_int;
rddata_reg(31) <= '0';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= regs_i.silen_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010001" =>
if (wb_we_i = '1') then
masterfip_tx_ctrl_rst_int <= wrdata_reg(0);
masterfip_tx_ctrl_start_int <= wrdata_reg(1);
masterfip_tx_ctrl_bytes_num_int <= wrdata_reg(23 downto 8);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= '0';
rddata_reg(23 downto 8) <= masterfip_tx_ctrl_bytes_num_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.tx_stat_stop_i;
rddata_reg(8) <= regs_i.tx_stat_ena_i;
rddata_reg(31 downto 16) <= regs_i.tx_stat_curr_byte_indx_i;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.fd_wdg_i;
rddata_reg(1) <= regs_i.fd_cd_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.fd_wdg_tstamp_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.fd_txer_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.fd_txer_tstamp_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010111" =>
if (wb_we_i = '1') then
masterfip_rx_ctrl_rst_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.rx_stat_pream_ok_i;
rddata_reg(1) <= regs_i.rx_stat_ctrl_byte_ok_i;
rddata_reg(2) <= regs_i.rx_stat_frame_ok_i;
rddata_reg(3) <= regs_i.rx_stat_frame_crc_err_i;
rddata_reg(4) <= regs_i.rx_stat_bytes_num_err_i;
rddata_reg(23 downto 8) <= regs_i.rx_stat_bytes_num_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.rx_stat_curr_word_indx_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat_crc_err_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.rx_payld_ctrl_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg4_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg5_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg6_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg7_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg8_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg9_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg10_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg11_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg12_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg13_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg14_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg15_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg16_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg17_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg18_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg19_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg20_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg21_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg22_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg23_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg24_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg25_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg26_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg27_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg28_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg29_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg30_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg31_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg32_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg33_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg34_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg35_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg36_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg37_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg38_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg39_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg40_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg41_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg42_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg43_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg44_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg45_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg46_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg47_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg48_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg49_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg50_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg51_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg52_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg53_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg54_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg55_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg56_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg57_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg58_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg59_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg60_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg61_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg62_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg63_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg64_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg65_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg66_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg67_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_ctrl_int <= wrdata_reg(7 downto 0);
end if;
rddata_reg(7 downto 0) <= masterfip_tx_payld_ctrl_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg1_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg1_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg2_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg2_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg3_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg3_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg4_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg4_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg5_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg5_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg6_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg6_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg7_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg7_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg8_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg8_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg9_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg9_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg10_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg10_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg11_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg11_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg12_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg12_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg13_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg13_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg14_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg14_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg15_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg15_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg16_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg16_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg17_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg17_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg18_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg18_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg19_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg19_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg20_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg20_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg21_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg21_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg22_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg22_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg23_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg23_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg24_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg24_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg25_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg25_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg26_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg26_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg27_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg27_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg28_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg28_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg29_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg29_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg30_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg30_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg31_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg31_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg32_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg32_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg33_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg33_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg34_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg34_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg35_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg35_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg36_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg36_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg37_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg37_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg38_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg38_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg39_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg39_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg40_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg40_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg41_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg41_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg42_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg42_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg43_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg43_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg44_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg44_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg45_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg45_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg46_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg46_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg47_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg47_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg48_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg48_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg49_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg49_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg50_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg50_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg51_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg51_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg52_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg52_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg53_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg53_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg54_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg54_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg55_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg55_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg56_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg56_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg57_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg57_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg58_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg58_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg59_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg59_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg60_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg60_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg61_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg61_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg62_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg62_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg63_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg63_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg64_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg64_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg65_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg65_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg66_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg66_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg67_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg67_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Version identifier
regs_o.ver_id_o <= masterfip_ver_id_int;
-- reset of the masterFIP core
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
masterfip_rst_core_dly0 <= '0';
regs_o.rst_core_o <= '0';
elsif rising_edge(clk_sys_i) then
masterfip_rst_core_dly0 <= masterfip_rst_core_int;
regs_o.rst_core_o <= masterfip_rst_core_int and (not masterfip_rst_core_dly0);
end if;
end process;
-- reset of the FielDrive chip
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
masterfip_rst_fd_dly0 <= '0';
regs_o.rst_fd_o <= '0';
elsif rising_edge(clk_sys_i) then
masterfip_rst_fd_dly0 <= masterfip_rst_fd_int;
regs_o.rst_fd_o <= masterfip_rst_fd_int and (not masterfip_rst_fd_dly0);
end if;
end process;
-- rx act green led
regs_o.led_rx_act_o <= masterfip_led_rx_act_int;
-- rx err red led
regs_o.led_rx_err_o <= masterfip_led_rx_err_int;
-- tx act green led
regs_o.led_tx_act_o <= masterfip_led_tx_act_int;
-- tx err red led
regs_o.led_tx_err_o <= masterfip_led_tx_err_int;
-- ext sync act green led
regs_o.led_ext_sync_act_o <= masterfip_led_ext_sync_act_int;
-- ext sync err red led
regs_o.led_ext_sync_err_o <= masterfip_led_ext_sync_err_int;
-- dbg
regs_o.led_dbg_o <= masterfip_led_dbg_int;
-- ds1820 temperature
-- ds1820 id lsb
-- ds1820 id msb
-- termination enable
regs_o.ext_sync_ctrl_term_en_o <= masterfip_ext_sync_ctrl_term_en_int;
-- transceiver direction
regs_o.ext_sync_ctrl_dir_o <= masterfip_ext_sync_ctrl_dir_int;
-- transceiver output enable negative logic
regs_o.ext_sync_ctrl_oe_n_o <= masterfip_ext_sync_ctrl_oe_n_int;
-- pulses counter reset
regs_o.ext_sync_ctrl_p_cnt_rst_o <= masterfip_ext_sync_ctrl_p_cnt_rst_int;
-- counting options
regs_o.ext_sync_ctrl_opt_o <= masterfip_ext_sync_ctrl_opt_int;
-- safe window
regs_o.ext_sync_ctrl_safe_wind_o <= masterfip_ext_sync_ctrl_safe_wind_int;
-- ext_sync_p_cnt
-- WorldFIP speed, hard-wired on the FMC
-- macrocycle lgth
regs_o.macrocyc_lgth_o <= masterfip_macrocyc_lgth_int;
-- macrocycle cnt start
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
masterfip_macrocyc_start_dly0 <= '0';
regs_o.macrocyc_start_o <= '0';
elsif rising_edge(clk_sys_i) then
masterfip_macrocyc_start_dly0 <= masterfip_macrocyc_start_int;
regs_o.macrocyc_start_o <= masterfip_macrocyc_start_int and (not masterfip_macrocyc_start_dly0);
end if;
end process;
-- macrocycle time counter
-- number of macrocycles
-- turnaround time
regs_o.turnar_lgth_o <= masterfip_turnar_lgth_int;
-- turnaround cnt start
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
masterfip_turnar_start_dly0 <= '0';
regs_o.turnar_start_o <= '0';
elsif rising_edge(clk_sys_i) then
masterfip_turnar_start_dly0 <= masterfip_turnar_start_int;
regs_o.turnar_start_o <= masterfip_turnar_start_int and (not masterfip_turnar_start_dly0);
end if;
end process;
-- turnaround time counter
-- silence time
regs_o.silen_lgth_o <= masterfip_silen_lgth_int;
-- silence cnt start
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
masterfip_silen_start_dly0 <= '0';
regs_o.silen_start_o <= '0';
elsif rising_edge(clk_sys_i) then
masterfip_silen_start_dly0 <= masterfip_silen_start_int;
regs_o.silen_start_o <= masterfip_silen_start_int and (not masterfip_silen_start_dly0);
end if;
end process;
-- silence time counter
-- tx rst
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
masterfip_tx_ctrl_rst_dly0 <= '0';
regs_o.tx_ctrl_rst_o <= '0';
elsif rising_edge(clk_sys_i) then
masterfip_tx_ctrl_rst_dly0 <= masterfip_tx_ctrl_rst_int;
regs_o.tx_ctrl_rst_o <= masterfip_tx_ctrl_rst_int and (not masterfip_tx_ctrl_rst_dly0);
end if;
end process;
-- tx strt
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
masterfip_tx_ctrl_start_dly0 <= '0';
regs_o.tx_ctrl_start_o <= '0';
elsif rising_edge(clk_sys_i) then
masterfip_tx_ctrl_start_dly0 <= masterfip_tx_ctrl_start_int;
regs_o.tx_ctrl_start_o <= masterfip_tx_ctrl_start_int and (not masterfip_tx_ctrl_start_dly0);
end if;
end process;
-- tx number of bytes
regs_o.tx_ctrl_bytes_num_o <= masterfip_tx_ctrl_bytes_num_int;
-- tx ended
-- tx enable
-- tx status current byte index
-- FielDrive watchdog
-- FielDrive carrier detect
-- fd_wdgn_tstamp
-- fd_txer_cnt
-- fd_txer_tstamp
-- rx rst
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
masterfip_rx_ctrl_rst_dly0 <= '0';
regs_o.rx_ctrl_rst_o <= '0';
elsif rising_edge(clk_sys_i) then
masterfip_rx_ctrl_rst_dly0 <= masterfip_rx_ctrl_rst_int;
regs_o.rx_ctrl_rst_o <= masterfip_rx_ctrl_rst_int and (not masterfip_rx_ctrl_rst_dly0);
end if;
end process;
-- rx Preamble(FSS) detected
-- rx CTRL byte detected
-- rx frame ok
-- rx frame crc error
-- rx bytes number error
-- rx number of payload bytes
-- current word index
-- rx number of frames with CRC error
-- rx payload ctrl byte
-- reg 1
-- reg2
-- reg3
-- reg4
-- reg5
-- reg6
-- reg7
-- reg8
-- reg9
-- reg10
-- reg11
-- reg12
-- reg13
-- reg14
-- reg15
-- reg16
-- reg17
-- reg18
-- reg19
-- reg20
-- reg21
-- reg22
-- reg23
-- reg24
-- reg25
-- reg26
-- reg27
-- reg28
-- reg29
-- reg30
-- reg31
-- reg32
-- reg 33
-- reg34
-- reg35
-- reg36
-- reg37
-- reg38
-- reg39
-- reg40
-- reg41
-- reg42
-- reg43
-- reg44
-- reg45
-- reg46
-- reg47
-- reg48
-- reg49
-- reg50
-- reg51
-- reg52
-- reg53
-- reg54
-- reg55
-- reg56
-- reg57
-- reg58
-- reg59
-- reg60
-- reg61
-- reg62
-- reg63
-- reg64
-- reg65
-- reg66
-- reg67
-- tx ctrl byte
regs_o.tx_payld_ctrl_o <= masterfip_tx_payld_ctrl_int;
-- reg1
regs_o.tx_payld_reg1_o <= masterfip_tx_payld_reg1_int;
-- reg2
regs_o.tx_payld_reg2_o <= masterfip_tx_payld_reg2_int;
-- reg3
regs_o.tx_payld_reg3_o <= masterfip_tx_payld_reg3_int;
-- reg4
regs_o.tx_payld_reg4_o <= masterfip_tx_payld_reg4_int;
-- reg5
regs_o.tx_payld_reg5_o <= masterfip_tx_payld_reg5_int;
-- reg6
regs_o.tx_payld_reg6_o <= masterfip_tx_payld_reg6_int;
-- reg7
regs_o.tx_payld_reg7_o <= masterfip_tx_payld_reg7_int;
-- reg8
regs_o.tx_payld_reg8_o <= masterfip_tx_payld_reg8_int;
-- reg9
regs_o.tx_payld_reg9_o <= masterfip_tx_payld_reg9_int;
-- reg10
regs_o.tx_payld_reg10_o <= masterfip_tx_payld_reg10_int;
-- reg11
regs_o.tx_payld_reg11_o <= masterfip_tx_payld_reg11_int;
-- reg12
regs_o.tx_payld_reg12_o <= masterfip_tx_payld_reg12_int;
-- reg13
regs_o.tx_payld_reg13_o <= masterfip_tx_payld_reg13_int;
-- reg14
regs_o.tx_payld_reg14_o <= masterfip_tx_payld_reg14_int;
-- reg15
regs_o.tx_payld_reg15_o <= masterfip_tx_payld_reg15_int;
-- reg16
regs_o.tx_payld_reg16_o <= masterfip_tx_payld_reg16_int;
-- reg17
regs_o.tx_payld_reg17_o <= masterfip_tx_payld_reg17_int;
-- reg18
regs_o.tx_payld_reg18_o <= masterfip_tx_payld_reg18_int;
-- reg19
regs_o.tx_payld_reg19_o <= masterfip_tx_payld_reg19_int;
-- reg20
regs_o.tx_payld_reg20_o <= masterfip_tx_payld_reg20_int;
-- reg21
regs_o.tx_payld_reg21_o <= masterfip_tx_payld_reg21_int;
-- reg22
regs_o.tx_payld_reg22_o <= masterfip_tx_payld_reg22_int;
-- reg23
regs_o.tx_payld_reg23_o <= masterfip_tx_payld_reg23_int;
-- reg24
regs_o.tx_payld_reg24_o <= masterfip_tx_payld_reg24_int;
-- reg25
regs_o.tx_payld_reg25_o <= masterfip_tx_payld_reg25_int;
-- reg26
regs_o.tx_payld_reg26_o <= masterfip_tx_payld_reg26_int;
-- reg27
regs_o.tx_payld_reg27_o <= masterfip_tx_payld_reg27_int;
-- reg28
regs_o.tx_payld_reg28_o <= masterfip_tx_payld_reg28_int;
-- reg29
regs_o.tx_payld_reg29_o <= masterfip_tx_payld_reg29_int;
-- reg30
regs_o.tx_payld_reg30_o <= masterfip_tx_payld_reg30_int;
-- reg31
regs_o.tx_payld_reg31_o <= masterfip_tx_payld_reg31_int;
-- reg32
regs_o.tx_payld_reg32_o <= masterfip_tx_payld_reg32_int;
-- reg 33
regs_o.tx_payld_reg33_o <= masterfip_tx_payld_reg33_int;
-- reg34
regs_o.tx_payld_reg34_o <= masterfip_tx_payld_reg34_int;
-- reg35
regs_o.tx_payld_reg35_o <= masterfip_tx_payld_reg35_int;
-- reg36
regs_o.tx_payld_reg36_o <= masterfip_tx_payld_reg36_int;
-- reg37
regs_o.tx_payld_reg37_o <= masterfip_tx_payld_reg37_int;
-- reg38
regs_o.tx_payld_reg38_o <= masterfip_tx_payld_reg38_int;
-- reg39
regs_o.tx_payld_reg39_o <= masterfip_tx_payld_reg39_int;
-- reg40
regs_o.tx_payld_reg40_o <= masterfip_tx_payld_reg40_int;
-- reg41
regs_o.tx_payld_reg41_o <= masterfip_tx_payld_reg41_int;
-- reg42
regs_o.tx_payld_reg42_o <= masterfip_tx_payld_reg42_int;
-- reg43
regs_o.tx_payld_reg43_o <= masterfip_tx_payld_reg43_int;
-- reg44
regs_o.tx_payld_reg44_o <= masterfip_tx_payld_reg44_int;
-- reg45
regs_o.tx_payld_reg45_o <= masterfip_tx_payld_reg45_int;
-- reg46
regs_o.tx_payld_reg46_o <= masterfip_tx_payld_reg46_int;
-- reg47
regs_o.tx_payld_reg47_o <= masterfip_tx_payld_reg47_int;
-- reg48
regs_o.tx_payld_reg48_o <= masterfip_tx_payld_reg48_int;
-- reg49
regs_o.tx_payld_reg49_o <= masterfip_tx_payld_reg49_int;
-- reg50
regs_o.tx_payld_reg50_o <= masterfip_tx_payld_reg50_int;
-- reg51
regs_o.tx_payld_reg51_o <= masterfip_tx_payld_reg51_int;
-- reg52
regs_o.tx_payld_reg52_o <= masterfip_tx_payld_reg52_int;
-- reg53
regs_o.tx_payld_reg53_o <= masterfip_tx_payld_reg53_int;
-- reg54
regs_o.tx_payld_reg54_o <= masterfip_tx_payld_reg54_int;
-- reg55
regs_o.tx_payld_reg55_o <= masterfip_tx_payld_reg55_int;
-- reg56
regs_o.tx_payld_reg56_o <= masterfip_tx_payld_reg56_int;
-- reg57
regs_o.tx_payld_reg57_o <= masterfip_tx_payld_reg57_int;
-- reg58
regs_o.tx_payld_reg58_o <= masterfip_tx_payld_reg58_int;
-- reg59
regs_o.tx_payld_reg59_o <= masterfip_tx_payld_reg59_int;
-- reg60
regs_o.tx_payld_reg60_o <= masterfip_tx_payld_reg60_int;
-- reg61
regs_o.tx_payld_reg61_o <= masterfip_tx_payld_reg61_int;
-- reg62
regs_o.tx_payld_reg62_o <= masterfip_tx_payld_reg62_int;
-- reg63
regs_o.tx_payld_reg63_o <= masterfip_tx_payld_reg63_int;
-- reg64
regs_o.tx_payld_reg64_o <= masterfip_tx_payld_reg64_int;
-- reg65
regs_o.tx_payld_reg65_o <= masterfip_tx_payld_reg65_int;
-- reg66
regs_o.tx_payld_reg66_o <= masterfip_tx_payld_reg66_int;
-- reg67
regs_o.tx_payld_reg67_o <= masterfip_tx_payld_reg67_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
masterfip-gw-adam-proposed_master/rtl/masterfip_wbgen2_pkg.vhd 0000664 0000000 0000000 00000100400 13422611646 0025172 0 ustar 00root root 0000000 0000000 ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC masterFIP core registers
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 07/17/17 17:07:34
-- Version : 0x00020000
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package masterfip_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_masterfip_in_registers is record
ds1820_temper_i : std_logic_vector(15 downto 0);
ds1820_id_lsb_i : std_logic_vector(31 downto 0);
ds1820_id_msb_i : std_logic_vector(31 downto 0);
ext_sync_p_cnt_i : std_logic_vector(31 downto 0);
speed_i : std_logic_vector(1 downto 0);
macrocyc_time_cnt_i : std_logic_vector(30 downto 0);
macrocyc_num_cnt_i : std_logic_vector(31 downto 0);
turnar_time_cnt_i : std_logic_vector(30 downto 0);
silen_time_cnt_i : std_logic_vector(30 downto 0);
tx_stat_stop_i : std_logic;
tx_stat_ena_i : std_logic;
tx_stat_curr_byte_indx_i : std_logic_vector(15 downto 0);
fd_wdg_i : std_logic;
fd_cd_i : std_logic;
fd_wdg_tstamp_i : std_logic_vector(31 downto 0);
fd_txer_cnt_i : std_logic_vector(31 downto 0);
fd_txer_tstamp_i : std_logic_vector(31 downto 0);
rx_stat_pream_ok_i : std_logic;
rx_stat_ctrl_byte_ok_i : std_logic;
rx_stat_frame_ok_i : std_logic;
rx_stat_frame_crc_err_i : std_logic;
rx_stat_bytes_num_err_i : std_logic;
rx_stat_bytes_num_i : std_logic_vector(15 downto 0);
rx_stat_curr_word_indx_i : std_logic_vector(7 downto 0);
rx_stat_crc_err_cnt_i : std_logic_vector(31 downto 0);
rx_payld_ctrl_i : std_logic_vector(7 downto 0);
rx_payld_reg1_i : std_logic_vector(31 downto 0);
rx_payld_reg2_i : std_logic_vector(31 downto 0);
rx_payld_reg3_i : std_logic_vector(31 downto 0);
rx_payld_reg4_i : std_logic_vector(31 downto 0);
rx_payld_reg5_i : std_logic_vector(31 downto 0);
rx_payld_reg6_i : std_logic_vector(31 downto 0);
rx_payld_reg7_i : std_logic_vector(31 downto 0);
rx_payld_reg8_i : std_logic_vector(31 downto 0);
rx_payld_reg9_i : std_logic_vector(31 downto 0);
rx_payld_reg10_i : std_logic_vector(31 downto 0);
rx_payld_reg11_i : std_logic_vector(31 downto 0);
rx_payld_reg12_i : std_logic_vector(31 downto 0);
rx_payld_reg13_i : std_logic_vector(31 downto 0);
rx_payld_reg14_i : std_logic_vector(31 downto 0);
rx_payld_reg15_i : std_logic_vector(31 downto 0);
rx_payld_reg16_i : std_logic_vector(31 downto 0);
rx_payld_reg17_i : std_logic_vector(31 downto 0);
rx_payld_reg18_i : std_logic_vector(31 downto 0);
rx_payld_reg19_i : std_logic_vector(31 downto 0);
rx_payld_reg20_i : std_logic_vector(31 downto 0);
rx_payld_reg21_i : std_logic_vector(31 downto 0);
rx_payld_reg22_i : std_logic_vector(31 downto 0);
rx_payld_reg23_i : std_logic_vector(31 downto 0);
rx_payld_reg24_i : std_logic_vector(31 downto 0);
rx_payld_reg25_i : std_logic_vector(31 downto 0);
rx_payld_reg26_i : std_logic_vector(31 downto 0);
rx_payld_reg27_i : std_logic_vector(31 downto 0);
rx_payld_reg28_i : std_logic_vector(31 downto 0);
rx_payld_reg29_i : std_logic_vector(31 downto 0);
rx_payld_reg30_i : std_logic_vector(31 downto 0);
rx_payld_reg31_i : std_logic_vector(31 downto 0);
rx_payld_reg32_i : std_logic_vector(31 downto 0);
rx_payld_reg33_i : std_logic_vector(31 downto 0);
rx_payld_reg34_i : std_logic_vector(31 downto 0);
rx_payld_reg35_i : std_logic_vector(31 downto 0);
rx_payld_reg36_i : std_logic_vector(31 downto 0);
rx_payld_reg37_i : std_logic_vector(31 downto 0);
rx_payld_reg38_i : std_logic_vector(31 downto 0);
rx_payld_reg39_i : std_logic_vector(31 downto 0);
rx_payld_reg40_i : std_logic_vector(31 downto 0);
rx_payld_reg41_i : std_logic_vector(31 downto 0);
rx_payld_reg42_i : std_logic_vector(31 downto 0);
rx_payld_reg43_i : std_logic_vector(31 downto 0);
rx_payld_reg44_i : std_logic_vector(31 downto 0);
rx_payld_reg45_i : std_logic_vector(31 downto 0);
rx_payld_reg46_i : std_logic_vector(31 downto 0);
rx_payld_reg47_i : std_logic_vector(31 downto 0);
rx_payld_reg48_i : std_logic_vector(31 downto 0);
rx_payld_reg49_i : std_logic_vector(31 downto 0);
rx_payld_reg50_i : std_logic_vector(31 downto 0);
rx_payld_reg51_i : std_logic_vector(31 downto 0);
rx_payld_reg52_i : std_logic_vector(31 downto 0);
rx_payld_reg53_i : std_logic_vector(31 downto 0);
rx_payld_reg54_i : std_logic_vector(31 downto 0);
rx_payld_reg55_i : std_logic_vector(31 downto 0);
rx_payld_reg56_i : std_logic_vector(31 downto 0);
rx_payld_reg57_i : std_logic_vector(31 downto 0);
rx_payld_reg58_i : std_logic_vector(31 downto 0);
rx_payld_reg59_i : std_logic_vector(31 downto 0);
rx_payld_reg60_i : std_logic_vector(31 downto 0);
rx_payld_reg61_i : std_logic_vector(31 downto 0);
rx_payld_reg62_i : std_logic_vector(31 downto 0);
rx_payld_reg63_i : std_logic_vector(31 downto 0);
rx_payld_reg64_i : std_logic_vector(31 downto 0);
rx_payld_reg65_i : std_logic_vector(31 downto 0);
rx_payld_reg66_i : std_logic_vector(31 downto 0);
rx_payld_reg67_i : std_logic_vector(31 downto 0);
end record;
constant c_masterfip_in_registers_init_value: t_masterfip_in_registers := (
ds1820_temper_i => (others => '0'),
ds1820_id_lsb_i => (others => '0'),
ds1820_id_msb_i => (others => '0'),
ext_sync_p_cnt_i => (others => '0'),
speed_i => (others => '0'),
macrocyc_time_cnt_i => (others => '0'),
macrocyc_num_cnt_i => (others => '0'),
turnar_time_cnt_i => (others => '0'),
silen_time_cnt_i => (others => '0'),
tx_stat_stop_i => '0',
tx_stat_ena_i => '0',
tx_stat_curr_byte_indx_i => (others => '0'),
fd_wdg_i => '0',
fd_cd_i => '0',
fd_wdg_tstamp_i => (others => '0'),
fd_txer_cnt_i => (others => '0'),
fd_txer_tstamp_i => (others => '0'),
rx_stat_pream_ok_i => '0',
rx_stat_ctrl_byte_ok_i => '0',
rx_stat_frame_ok_i => '0',
rx_stat_frame_crc_err_i => '0',
rx_stat_bytes_num_err_i => '0',
rx_stat_bytes_num_i => (others => '0'),
rx_stat_curr_word_indx_i => (others => '0'),
rx_stat_crc_err_cnt_i => (others => '0'),
rx_payld_ctrl_i => (others => '0'),
rx_payld_reg1_i => (others => '0'),
rx_payld_reg2_i => (others => '0'),
rx_payld_reg3_i => (others => '0'),
rx_payld_reg4_i => (others => '0'),
rx_payld_reg5_i => (others => '0'),
rx_payld_reg6_i => (others => '0'),
rx_payld_reg7_i => (others => '0'),
rx_payld_reg8_i => (others => '0'),
rx_payld_reg9_i => (others => '0'),
rx_payld_reg10_i => (others => '0'),
rx_payld_reg11_i => (others => '0'),
rx_payld_reg12_i => (others => '0'),
rx_payld_reg13_i => (others => '0'),
rx_payld_reg14_i => (others => '0'),
rx_payld_reg15_i => (others => '0'),
rx_payld_reg16_i => (others => '0'),
rx_payld_reg17_i => (others => '0'),
rx_payld_reg18_i => (others => '0'),
rx_payld_reg19_i => (others => '0'),
rx_payld_reg20_i => (others => '0'),
rx_payld_reg21_i => (others => '0'),
rx_payld_reg22_i => (others => '0'),
rx_payld_reg23_i => (others => '0'),
rx_payld_reg24_i => (others => '0'),
rx_payld_reg25_i => (others => '0'),
rx_payld_reg26_i => (others => '0'),
rx_payld_reg27_i => (others => '0'),
rx_payld_reg28_i => (others => '0'),
rx_payld_reg29_i => (others => '0'),
rx_payld_reg30_i => (others => '0'),
rx_payld_reg31_i => (others => '0'),
rx_payld_reg32_i => (others => '0'),
rx_payld_reg33_i => (others => '0'),
rx_payld_reg34_i => (others => '0'),
rx_payld_reg35_i => (others => '0'),
rx_payld_reg36_i => (others => '0'),
rx_payld_reg37_i => (others => '0'),
rx_payld_reg38_i => (others => '0'),
rx_payld_reg39_i => (others => '0'),
rx_payld_reg40_i => (others => '0'),
rx_payld_reg41_i => (others => '0'),
rx_payld_reg42_i => (others => '0'),
rx_payld_reg43_i => (others => '0'),
rx_payld_reg44_i => (others => '0'),
rx_payld_reg45_i => (others => '0'),
rx_payld_reg46_i => (others => '0'),
rx_payld_reg47_i => (others => '0'),
rx_payld_reg48_i => (others => '0'),
rx_payld_reg49_i => (others => '0'),
rx_payld_reg50_i => (others => '0'),
rx_payld_reg51_i => (others => '0'),
rx_payld_reg52_i => (others => '0'),
rx_payld_reg53_i => (others => '0'),
rx_payld_reg54_i => (others => '0'),
rx_payld_reg55_i => (others => '0'),
rx_payld_reg56_i => (others => '0'),
rx_payld_reg57_i => (others => '0'),
rx_payld_reg58_i => (others => '0'),
rx_payld_reg59_i => (others => '0'),
rx_payld_reg60_i => (others => '0'),
rx_payld_reg61_i => (others => '0'),
rx_payld_reg62_i => (others => '0'),
rx_payld_reg63_i => (others => '0'),
rx_payld_reg64_i => (others => '0'),
rx_payld_reg65_i => (others => '0'),
rx_payld_reg66_i => (others => '0'),
rx_payld_reg67_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_masterfip_out_registers is record
ver_id_o : std_logic_vector(31 downto 0);
rst_core_o : std_logic;
rst_fd_o : std_logic;
led_rx_act_o : std_logic;
led_rx_err_o : std_logic;
led_tx_act_o : std_logic;
led_tx_err_o : std_logic;
led_ext_sync_act_o : std_logic;
led_ext_sync_err_o : std_logic;
led_dbg_o : std_logic_vector(23 downto 0);
ext_sync_ctrl_term_en_o : std_logic;
ext_sync_ctrl_dir_o : std_logic;
ext_sync_ctrl_oe_n_o : std_logic;
ext_sync_ctrl_p_cnt_rst_o : std_logic;
ext_sync_ctrl_opt_o : std_logic;
ext_sync_ctrl_safe_wind_o : std_logic;
macrocyc_lgth_o : std_logic_vector(30 downto 0);
macrocyc_start_o : std_logic;
turnar_lgth_o : std_logic_vector(30 downto 0);
turnar_start_o : std_logic;
silen_lgth_o : std_logic_vector(30 downto 0);
silen_start_o : std_logic;
tx_ctrl_rst_o : std_logic;
tx_ctrl_start_o : std_logic;
tx_ctrl_bytes_num_o : std_logic_vector(15 downto 0);
rx_ctrl_rst_o : std_logic;
tx_payld_ctrl_o : std_logic_vector(7 downto 0);
tx_payld_reg1_o : std_logic_vector(31 downto 0);
tx_payld_reg2_o : std_logic_vector(31 downto 0);
tx_payld_reg3_o : std_logic_vector(31 downto 0);
tx_payld_reg4_o : std_logic_vector(31 downto 0);
tx_payld_reg5_o : std_logic_vector(31 downto 0);
tx_payld_reg6_o : std_logic_vector(31 downto 0);
tx_payld_reg7_o : std_logic_vector(31 downto 0);
tx_payld_reg8_o : std_logic_vector(31 downto 0);
tx_payld_reg9_o : std_logic_vector(31 downto 0);
tx_payld_reg10_o : std_logic_vector(31 downto 0);
tx_payld_reg11_o : std_logic_vector(31 downto 0);
tx_payld_reg12_o : std_logic_vector(31 downto 0);
tx_payld_reg13_o : std_logic_vector(31 downto 0);
tx_payld_reg14_o : std_logic_vector(31 downto 0);
tx_payld_reg15_o : std_logic_vector(31 downto 0);
tx_payld_reg16_o : std_logic_vector(31 downto 0);
tx_payld_reg17_o : std_logic_vector(31 downto 0);
tx_payld_reg18_o : std_logic_vector(31 downto 0);
tx_payld_reg19_o : std_logic_vector(31 downto 0);
tx_payld_reg20_o : std_logic_vector(31 downto 0);
tx_payld_reg21_o : std_logic_vector(31 downto 0);
tx_payld_reg22_o : std_logic_vector(31 downto 0);
tx_payld_reg23_o : std_logic_vector(31 downto 0);
tx_payld_reg24_o : std_logic_vector(31 downto 0);
tx_payld_reg25_o : std_logic_vector(31 downto 0);
tx_payld_reg26_o : std_logic_vector(31 downto 0);
tx_payld_reg27_o : std_logic_vector(31 downto 0);
tx_payld_reg28_o : std_logic_vector(31 downto 0);
tx_payld_reg29_o : std_logic_vector(31 downto 0);
tx_payld_reg30_o : std_logic_vector(31 downto 0);
tx_payld_reg31_o : std_logic_vector(31 downto 0);
tx_payld_reg32_o : std_logic_vector(31 downto 0);
tx_payld_reg33_o : std_logic_vector(31 downto 0);
tx_payld_reg34_o : std_logic_vector(31 downto 0);
tx_payld_reg35_o : std_logic_vector(31 downto 0);
tx_payld_reg36_o : std_logic_vector(31 downto 0);
tx_payld_reg37_o : std_logic_vector(31 downto 0);
tx_payld_reg38_o : std_logic_vector(31 downto 0);
tx_payld_reg39_o : std_logic_vector(31 downto 0);
tx_payld_reg40_o : std_logic_vector(31 downto 0);
tx_payld_reg41_o : std_logic_vector(31 downto 0);
tx_payld_reg42_o : std_logic_vector(31 downto 0);
tx_payld_reg43_o : std_logic_vector(31 downto 0);
tx_payld_reg44_o : std_logic_vector(31 downto 0);
tx_payld_reg45_o : std_logic_vector(31 downto 0);
tx_payld_reg46_o : std_logic_vector(31 downto 0);
tx_payld_reg47_o : std_logic_vector(31 downto 0);
tx_payld_reg48_o : std_logic_vector(31 downto 0);
tx_payld_reg49_o : std_logic_vector(31 downto 0);
tx_payld_reg50_o : std_logic_vector(31 downto 0);
tx_payld_reg51_o : std_logic_vector(31 downto 0);
tx_payld_reg52_o : std_logic_vector(31 downto 0);
tx_payld_reg53_o : std_logic_vector(31 downto 0);
tx_payld_reg54_o : std_logic_vector(31 downto 0);
tx_payld_reg55_o : std_logic_vector(31 downto 0);
tx_payld_reg56_o : std_logic_vector(31 downto 0);
tx_payld_reg57_o : std_logic_vector(31 downto 0);
tx_payld_reg58_o : std_logic_vector(31 downto 0);
tx_payld_reg59_o : std_logic_vector(31 downto 0);
tx_payld_reg60_o : std_logic_vector(31 downto 0);
tx_payld_reg61_o : std_logic_vector(31 downto 0);
tx_payld_reg62_o : std_logic_vector(31 downto 0);
tx_payld_reg63_o : std_logic_vector(31 downto 0);
tx_payld_reg64_o : std_logic_vector(31 downto 0);
tx_payld_reg65_o : std_logic_vector(31 downto 0);
tx_payld_reg66_o : std_logic_vector(31 downto 0);
tx_payld_reg67_o : std_logic_vector(31 downto 0);
end record;
constant c_masterfip_out_registers_init_value: t_masterfip_out_registers := (
ver_id_o => (others => '0'),
rst_core_o => '0',
rst_fd_o => '0',
led_rx_act_o => '0',
led_rx_err_o => '0',
led_tx_act_o => '0',
led_tx_err_o => '0',
led_ext_sync_act_o => '0',
led_ext_sync_err_o => '0',
led_dbg_o => (others => '0'),
ext_sync_ctrl_term_en_o => '0',
ext_sync_ctrl_dir_o => '0',
ext_sync_ctrl_oe_n_o => '0',
ext_sync_ctrl_p_cnt_rst_o => '0',
ext_sync_ctrl_opt_o => '0',
ext_sync_ctrl_safe_wind_o => '0',
macrocyc_lgth_o => (others => '0'),
macrocyc_start_o => '0',
turnar_lgth_o => (others => '0'),
turnar_start_o => '0',
silen_lgth_o => (others => '0'),
silen_start_o => '0',
tx_ctrl_rst_o => '0',
tx_ctrl_start_o => '0',
tx_ctrl_bytes_num_o => (others => '0'),
rx_ctrl_rst_o => '0',
tx_payld_ctrl_o => (others => '0'),
tx_payld_reg1_o => (others => '0'),
tx_payld_reg2_o => (others => '0'),
tx_payld_reg3_o => (others => '0'),
tx_payld_reg4_o => (others => '0'),
tx_payld_reg5_o => (others => '0'),
tx_payld_reg6_o => (others => '0'),
tx_payld_reg7_o => (others => '0'),
tx_payld_reg8_o => (others => '0'),
tx_payld_reg9_o => (others => '0'),
tx_payld_reg10_o => (others => '0'),
tx_payld_reg11_o => (others => '0'),
tx_payld_reg12_o => (others => '0'),
tx_payld_reg13_o => (others => '0'),
tx_payld_reg14_o => (others => '0'),
tx_payld_reg15_o => (others => '0'),
tx_payld_reg16_o => (others => '0'),
tx_payld_reg17_o => (others => '0'),
tx_payld_reg18_o => (others => '0'),
tx_payld_reg19_o => (others => '0'),
tx_payld_reg20_o => (others => '0'),
tx_payld_reg21_o => (others => '0'),
tx_payld_reg22_o => (others => '0'),
tx_payld_reg23_o => (others => '0'),
tx_payld_reg24_o => (others => '0'),
tx_payld_reg25_o => (others => '0'),
tx_payld_reg26_o => (others => '0'),
tx_payld_reg27_o => (others => '0'),
tx_payld_reg28_o => (others => '0'),
tx_payld_reg29_o => (others => '0'),
tx_payld_reg30_o => (others => '0'),
tx_payld_reg31_o => (others => '0'),
tx_payld_reg32_o => (others => '0'),
tx_payld_reg33_o => (others => '0'),
tx_payld_reg34_o => (others => '0'),
tx_payld_reg35_o => (others => '0'),
tx_payld_reg36_o => (others => '0'),
tx_payld_reg37_o => (others => '0'),
tx_payld_reg38_o => (others => '0'),
tx_payld_reg39_o => (others => '0'),
tx_payld_reg40_o => (others => '0'),
tx_payld_reg41_o => (others => '0'),
tx_payld_reg42_o => (others => '0'),
tx_payld_reg43_o => (others => '0'),
tx_payld_reg44_o => (others => '0'),
tx_payld_reg45_o => (others => '0'),
tx_payld_reg46_o => (others => '0'),
tx_payld_reg47_o => (others => '0'),
tx_payld_reg48_o => (others => '0'),
tx_payld_reg49_o => (others => '0'),
tx_payld_reg50_o => (others => '0'),
tx_payld_reg51_o => (others => '0'),
tx_payld_reg52_o => (others => '0'),
tx_payld_reg53_o => (others => '0'),
tx_payld_reg54_o => (others => '0'),
tx_payld_reg55_o => (others => '0'),
tx_payld_reg56_o => (others => '0'),
tx_payld_reg57_o => (others => '0'),
tx_payld_reg58_o => (others => '0'),
tx_payld_reg59_o => (others => '0'),
tx_payld_reg60_o => (others => '0'),
tx_payld_reg61_o => (others => '0'),
tx_payld_reg62_o => (others => '0'),
tx_payld_reg63_o => (others => '0'),
tx_payld_reg64_o => (others => '0'),
tx_payld_reg65_o => (others => '0'),
tx_payld_reg66_o => (others => '0'),
tx_payld_reg67_o => (others => '0')
);
function "or" (left, right: t_masterfip_in_registers) return t_masterfip_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body masterfip_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_masterfip_in_registers) return t_masterfip_in_registers is
variable tmp: t_masterfip_in_registers;
begin
tmp.ds1820_temper_i := f_x_to_zero(left.ds1820_temper_i) or f_x_to_zero(right.ds1820_temper_i);
tmp.ds1820_id_lsb_i := f_x_to_zero(left.ds1820_id_lsb_i) or f_x_to_zero(right.ds1820_id_lsb_i);
tmp.ds1820_id_msb_i := f_x_to_zero(left.ds1820_id_msb_i) or f_x_to_zero(right.ds1820_id_msb_i);
tmp.ext_sync_p_cnt_i := f_x_to_zero(left.ext_sync_p_cnt_i) or f_x_to_zero(right.ext_sync_p_cnt_i);
tmp.speed_i := f_x_to_zero(left.speed_i) or f_x_to_zero(right.speed_i);
tmp.macrocyc_time_cnt_i := f_x_to_zero(left.macrocyc_time_cnt_i) or f_x_to_zero(right.macrocyc_time_cnt_i);
tmp.macrocyc_num_cnt_i := f_x_to_zero(left.macrocyc_num_cnt_i) or f_x_to_zero(right.macrocyc_num_cnt_i);
tmp.turnar_time_cnt_i := f_x_to_zero(left.turnar_time_cnt_i) or f_x_to_zero(right.turnar_time_cnt_i);
tmp.silen_time_cnt_i := f_x_to_zero(left.silen_time_cnt_i) or f_x_to_zero(right.silen_time_cnt_i);
tmp.tx_stat_stop_i := f_x_to_zero(left.tx_stat_stop_i) or f_x_to_zero(right.tx_stat_stop_i);
tmp.tx_stat_ena_i := f_x_to_zero(left.tx_stat_ena_i) or f_x_to_zero(right.tx_stat_ena_i);
tmp.tx_stat_curr_byte_indx_i := f_x_to_zero(left.tx_stat_curr_byte_indx_i) or f_x_to_zero(right.tx_stat_curr_byte_indx_i);
tmp.fd_wdg_i := f_x_to_zero(left.fd_wdg_i) or f_x_to_zero(right.fd_wdg_i);
tmp.fd_cd_i := f_x_to_zero(left.fd_cd_i) or f_x_to_zero(right.fd_cd_i);
tmp.fd_wdg_tstamp_i := f_x_to_zero(left.fd_wdg_tstamp_i) or f_x_to_zero(right.fd_wdg_tstamp_i);
tmp.fd_txer_cnt_i := f_x_to_zero(left.fd_txer_cnt_i) or f_x_to_zero(right.fd_txer_cnt_i);
tmp.fd_txer_tstamp_i := f_x_to_zero(left.fd_txer_tstamp_i) or f_x_to_zero(right.fd_txer_tstamp_i);
tmp.rx_stat_pream_ok_i := f_x_to_zero(left.rx_stat_pream_ok_i) or f_x_to_zero(right.rx_stat_pream_ok_i);
tmp.rx_stat_ctrl_byte_ok_i := f_x_to_zero(left.rx_stat_ctrl_byte_ok_i) or f_x_to_zero(right.rx_stat_ctrl_byte_ok_i);
tmp.rx_stat_frame_ok_i := f_x_to_zero(left.rx_stat_frame_ok_i) or f_x_to_zero(right.rx_stat_frame_ok_i);
tmp.rx_stat_frame_crc_err_i := f_x_to_zero(left.rx_stat_frame_crc_err_i) or f_x_to_zero(right.rx_stat_frame_crc_err_i);
tmp.rx_stat_bytes_num_err_i := f_x_to_zero(left.rx_stat_bytes_num_err_i) or f_x_to_zero(right.rx_stat_bytes_num_err_i);
tmp.rx_stat_bytes_num_i := f_x_to_zero(left.rx_stat_bytes_num_i) or f_x_to_zero(right.rx_stat_bytes_num_i);
tmp.rx_stat_curr_word_indx_i := f_x_to_zero(left.rx_stat_curr_word_indx_i) or f_x_to_zero(right.rx_stat_curr_word_indx_i);
tmp.rx_stat_crc_err_cnt_i := f_x_to_zero(left.rx_stat_crc_err_cnt_i) or f_x_to_zero(right.rx_stat_crc_err_cnt_i);
tmp.rx_payld_ctrl_i := f_x_to_zero(left.rx_payld_ctrl_i) or f_x_to_zero(right.rx_payld_ctrl_i);
tmp.rx_payld_reg1_i := f_x_to_zero(left.rx_payld_reg1_i) or f_x_to_zero(right.rx_payld_reg1_i);
tmp.rx_payld_reg2_i := f_x_to_zero(left.rx_payld_reg2_i) or f_x_to_zero(right.rx_payld_reg2_i);
tmp.rx_payld_reg3_i := f_x_to_zero(left.rx_payld_reg3_i) or f_x_to_zero(right.rx_payld_reg3_i);
tmp.rx_payld_reg4_i := f_x_to_zero(left.rx_payld_reg4_i) or f_x_to_zero(right.rx_payld_reg4_i);
tmp.rx_payld_reg5_i := f_x_to_zero(left.rx_payld_reg5_i) or f_x_to_zero(right.rx_payld_reg5_i);
tmp.rx_payld_reg6_i := f_x_to_zero(left.rx_payld_reg6_i) or f_x_to_zero(right.rx_payld_reg6_i);
tmp.rx_payld_reg7_i := f_x_to_zero(left.rx_payld_reg7_i) or f_x_to_zero(right.rx_payld_reg7_i);
tmp.rx_payld_reg8_i := f_x_to_zero(left.rx_payld_reg8_i) or f_x_to_zero(right.rx_payld_reg8_i);
tmp.rx_payld_reg9_i := f_x_to_zero(left.rx_payld_reg9_i) or f_x_to_zero(right.rx_payld_reg9_i);
tmp.rx_payld_reg10_i := f_x_to_zero(left.rx_payld_reg10_i) or f_x_to_zero(right.rx_payld_reg10_i);
tmp.rx_payld_reg11_i := f_x_to_zero(left.rx_payld_reg11_i) or f_x_to_zero(right.rx_payld_reg11_i);
tmp.rx_payld_reg12_i := f_x_to_zero(left.rx_payld_reg12_i) or f_x_to_zero(right.rx_payld_reg12_i);
tmp.rx_payld_reg13_i := f_x_to_zero(left.rx_payld_reg13_i) or f_x_to_zero(right.rx_payld_reg13_i);
tmp.rx_payld_reg14_i := f_x_to_zero(left.rx_payld_reg14_i) or f_x_to_zero(right.rx_payld_reg14_i);
tmp.rx_payld_reg15_i := f_x_to_zero(left.rx_payld_reg15_i) or f_x_to_zero(right.rx_payld_reg15_i);
tmp.rx_payld_reg16_i := f_x_to_zero(left.rx_payld_reg16_i) or f_x_to_zero(right.rx_payld_reg16_i);
tmp.rx_payld_reg17_i := f_x_to_zero(left.rx_payld_reg17_i) or f_x_to_zero(right.rx_payld_reg17_i);
tmp.rx_payld_reg18_i := f_x_to_zero(left.rx_payld_reg18_i) or f_x_to_zero(right.rx_payld_reg18_i);
tmp.rx_payld_reg19_i := f_x_to_zero(left.rx_payld_reg19_i) or f_x_to_zero(right.rx_payld_reg19_i);
tmp.rx_payld_reg20_i := f_x_to_zero(left.rx_payld_reg20_i) or f_x_to_zero(right.rx_payld_reg20_i);
tmp.rx_payld_reg21_i := f_x_to_zero(left.rx_payld_reg21_i) or f_x_to_zero(right.rx_payld_reg21_i);
tmp.rx_payld_reg22_i := f_x_to_zero(left.rx_payld_reg22_i) or f_x_to_zero(right.rx_payld_reg22_i);
tmp.rx_payld_reg23_i := f_x_to_zero(left.rx_payld_reg23_i) or f_x_to_zero(right.rx_payld_reg23_i);
tmp.rx_payld_reg24_i := f_x_to_zero(left.rx_payld_reg24_i) or f_x_to_zero(right.rx_payld_reg24_i);
tmp.rx_payld_reg25_i := f_x_to_zero(left.rx_payld_reg25_i) or f_x_to_zero(right.rx_payld_reg25_i);
tmp.rx_payld_reg26_i := f_x_to_zero(left.rx_payld_reg26_i) or f_x_to_zero(right.rx_payld_reg26_i);
tmp.rx_payld_reg27_i := f_x_to_zero(left.rx_payld_reg27_i) or f_x_to_zero(right.rx_payld_reg27_i);
tmp.rx_payld_reg28_i := f_x_to_zero(left.rx_payld_reg28_i) or f_x_to_zero(right.rx_payld_reg28_i);
tmp.rx_payld_reg29_i := f_x_to_zero(left.rx_payld_reg29_i) or f_x_to_zero(right.rx_payld_reg29_i);
tmp.rx_payld_reg30_i := f_x_to_zero(left.rx_payld_reg30_i) or f_x_to_zero(right.rx_payld_reg30_i);
tmp.rx_payld_reg31_i := f_x_to_zero(left.rx_payld_reg31_i) or f_x_to_zero(right.rx_payld_reg31_i);
tmp.rx_payld_reg32_i := f_x_to_zero(left.rx_payld_reg32_i) or f_x_to_zero(right.rx_payld_reg32_i);
tmp.rx_payld_reg33_i := f_x_to_zero(left.rx_payld_reg33_i) or f_x_to_zero(right.rx_payld_reg33_i);
tmp.rx_payld_reg34_i := f_x_to_zero(left.rx_payld_reg34_i) or f_x_to_zero(right.rx_payld_reg34_i);
tmp.rx_payld_reg35_i := f_x_to_zero(left.rx_payld_reg35_i) or f_x_to_zero(right.rx_payld_reg35_i);
tmp.rx_payld_reg36_i := f_x_to_zero(left.rx_payld_reg36_i) or f_x_to_zero(right.rx_payld_reg36_i);
tmp.rx_payld_reg37_i := f_x_to_zero(left.rx_payld_reg37_i) or f_x_to_zero(right.rx_payld_reg37_i);
tmp.rx_payld_reg38_i := f_x_to_zero(left.rx_payld_reg38_i) or f_x_to_zero(right.rx_payld_reg38_i);
tmp.rx_payld_reg39_i := f_x_to_zero(left.rx_payld_reg39_i) or f_x_to_zero(right.rx_payld_reg39_i);
tmp.rx_payld_reg40_i := f_x_to_zero(left.rx_payld_reg40_i) or f_x_to_zero(right.rx_payld_reg40_i);
tmp.rx_payld_reg41_i := f_x_to_zero(left.rx_payld_reg41_i) or f_x_to_zero(right.rx_payld_reg41_i);
tmp.rx_payld_reg42_i := f_x_to_zero(left.rx_payld_reg42_i) or f_x_to_zero(right.rx_payld_reg42_i);
tmp.rx_payld_reg43_i := f_x_to_zero(left.rx_payld_reg43_i) or f_x_to_zero(right.rx_payld_reg43_i);
tmp.rx_payld_reg44_i := f_x_to_zero(left.rx_payld_reg44_i) or f_x_to_zero(right.rx_payld_reg44_i);
tmp.rx_payld_reg45_i := f_x_to_zero(left.rx_payld_reg45_i) or f_x_to_zero(right.rx_payld_reg45_i);
tmp.rx_payld_reg46_i := f_x_to_zero(left.rx_payld_reg46_i) or f_x_to_zero(right.rx_payld_reg46_i);
tmp.rx_payld_reg47_i := f_x_to_zero(left.rx_payld_reg47_i) or f_x_to_zero(right.rx_payld_reg47_i);
tmp.rx_payld_reg48_i := f_x_to_zero(left.rx_payld_reg48_i) or f_x_to_zero(right.rx_payld_reg48_i);
tmp.rx_payld_reg49_i := f_x_to_zero(left.rx_payld_reg49_i) or f_x_to_zero(right.rx_payld_reg49_i);
tmp.rx_payld_reg50_i := f_x_to_zero(left.rx_payld_reg50_i) or f_x_to_zero(right.rx_payld_reg50_i);
tmp.rx_payld_reg51_i := f_x_to_zero(left.rx_payld_reg51_i) or f_x_to_zero(right.rx_payld_reg51_i);
tmp.rx_payld_reg52_i := f_x_to_zero(left.rx_payld_reg52_i) or f_x_to_zero(right.rx_payld_reg52_i);
tmp.rx_payld_reg53_i := f_x_to_zero(left.rx_payld_reg53_i) or f_x_to_zero(right.rx_payld_reg53_i);
tmp.rx_payld_reg54_i := f_x_to_zero(left.rx_payld_reg54_i) or f_x_to_zero(right.rx_payld_reg54_i);
tmp.rx_payld_reg55_i := f_x_to_zero(left.rx_payld_reg55_i) or f_x_to_zero(right.rx_payld_reg55_i);
tmp.rx_payld_reg56_i := f_x_to_zero(left.rx_payld_reg56_i) or f_x_to_zero(right.rx_payld_reg56_i);
tmp.rx_payld_reg57_i := f_x_to_zero(left.rx_payld_reg57_i) or f_x_to_zero(right.rx_payld_reg57_i);
tmp.rx_payld_reg58_i := f_x_to_zero(left.rx_payld_reg58_i) or f_x_to_zero(right.rx_payld_reg58_i);
tmp.rx_payld_reg59_i := f_x_to_zero(left.rx_payld_reg59_i) or f_x_to_zero(right.rx_payld_reg59_i);
tmp.rx_payld_reg60_i := f_x_to_zero(left.rx_payld_reg60_i) or f_x_to_zero(right.rx_payld_reg60_i);
tmp.rx_payld_reg61_i := f_x_to_zero(left.rx_payld_reg61_i) or f_x_to_zero(right.rx_payld_reg61_i);
tmp.rx_payld_reg62_i := f_x_to_zero(left.rx_payld_reg62_i) or f_x_to_zero(right.rx_payld_reg62_i);
tmp.rx_payld_reg63_i := f_x_to_zero(left.rx_payld_reg63_i) or f_x_to_zero(right.rx_payld_reg63_i);
tmp.rx_payld_reg64_i := f_x_to_zero(left.rx_payld_reg64_i) or f_x_to_zero(right.rx_payld_reg64_i);
tmp.rx_payld_reg65_i := f_x_to_zero(left.rx_payld_reg65_i) or f_x_to_zero(right.rx_payld_reg65_i);
tmp.rx_payld_reg66_i := f_x_to_zero(left.rx_payld_reg66_i) or f_x_to_zero(right.rx_payld_reg66_i);
tmp.rx_payld_reg67_i := f_x_to_zero(left.rx_payld_reg67_i) or f_x_to_zero(right.rx_payld_reg67_i);
return tmp;
end function;
end package body;
masterfip-gw-adam-proposed_master/rtl/wbgen/ 0000775 0000000 0000000 00000000000 13422611646 0021477 5 ustar 00root root 0000000 0000000 masterfip-gw-adam-proposed_master/rtl/wbgen/build_from_wb.sh 0000664 0000000 0000000 00000000504 13422611646 0024644 0 ustar 00root root 0000000 0000000 #!/bin/bash
wbgen2 -V masterfip_wbgen2_csr.vhd -H record -p masterfip_wbgen2_pkg.vhd -s defines -C masterfip_wbgen2_csr.h -D masterfip_wbgen2_csr.html masterfip_csr.wb
echo ""
echo "Moving wbgen2 generated files to the following locations..."
echo ""
mv -v ./master_wbgen2_csr.vhd ../.
mv -v ./master_wbgen2_pkg.vhd ../.
masterfip-gw-adam-proposed_master/rtl/wbgen/masterfip_csr.wb 0000664 0000000 0000000 00000207156 13422611646 0024705 0 ustar 00root root 0000000 0000000 peripheral {
name = "FMC masterFIP core registers";
description = "Wishbone slave for FMC masterFIP core";
hdl_entity = "masterfip_wbgen2_csr";
prefix = "masterfip";
version = 0x020000; -- major: 02 minor: 00 micro: 00
-- Note that for html readability, some of the lines are longer than 100 characters.
----------------------------------------------------------------------------------------------------
-- RESET --
----------------------------------------------------------------------------------------------------
reg {
name = "rst";
prefix = "rst";
description = "software reset of the masterFIP core";
field {
name = "reset of the masterFIP core";
description = "write 1: generates a 1-clk-tick-long (10ns) masterFIP core reset;\
note: there is no need to clear the bit before writing another '1';\
it s also not meaningful to read back this register";
type = MONOSTABLE;
prefix = "core";
};
field {
name = "reset of the FielDrive chip";
description = "write 1: to generate a FielDrive reset;\
upon writing, the fmc_masterFIP_core generates a 1-WorldFIP-clk-tick-long FD RSTN;\
note: there is no need to clear the bit before writing another '1';\
it s also not meaningful to read back this register";
type = MONOSTABLE;
prefix = "fd";
};
};
----------------------------------------------------------------------------------------------------
-- CORE IDENTIFIER --
----------------------------------------------------------------------------------------------------
reg {
name = "core id";
description = "constant identification value: C000FFEE";
prefix = "id";
field {
name = "an id value";
description = "equal to 0xC000FFEE
";
size = 32;
type = CONSTANT;
value = 0xC000FFEE;
};
};
----------------------------------------------------------------------------------------------------
-- LEDs and DEBUGGING --
----------------------------------------------------------------------------------------------------
reg {
name = "leds and debug";
description = "managing of the front panel LEDs of the masterFIP mezzanine;\
note that if an application is not using synchronisation through the LEMO EXT SYNC,\
the EXT_SYNC_ACT and EXT_SYNC_ERR LEDs will be both switched off.\
Note also that the remaining bits of this register are used for debugging purposes";
prefix = "led";
field {
name = "rx act green led";
prefix = "rx_act";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "rx err red led";
prefix = "rx_err";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "tx act green led";
prefix = "tx_act";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "tx err red led";
prefix = "tx_err";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ext sync act green led";
prefix = "ext_sync_act";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ext sync err red led";
prefix = "ext_sync_err";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "dbg";
prefix = "dbg";
description = "bit 8 is connected to TP3; bit 9 is connected to TP4";
size = 24;
align = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
----------------------------------------------------------------------------------------------------
-- DS1820 ONE WIRE --
----------------------------------------------------------------------------------------------------
reg {
name = "fmc temperature";
description = "raw temperature data from the one wire DS18B20U+;\
the register is 2-bytes long; it translates to oC as follows:\
temp = ((byte1 << 8) | byte0) / 16.0";
prefix = "ds1820_temper";
field {
name = "ds1820 temperature";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "fmc unique id lsb";
description = "id (lsb) read from the one wire DS18B20U+";
prefix = "ds1820_id_lsb";
field {
name = "ds1820 id lsb";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "fmc unique id msb";
description = "id (msb) read from the one wire DS18B20U+";
prefix = "ds1820_id_msb";
field {
name = "ds1820 id msb";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
----------------------------------------------------------------------------------------------------
-- EXT SYNC PULSE --
----------------------------------------------------------------------------------------------------
reg {
name = "ext sync ctrl";
prefix = "ext_sync_ctrl";
field {
name = "termination enable";
prefix = "term_en";
description = "write 0: disable 50ohms termination of the external sync pulse\
write 1: enable 50ohms termination of the external sync pulse";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "transceiver direction";
prefix = "dir";
description = "write 0: normal operation\
write 1: test mode where a pulse from the FPGA can be output to the front panel LEMO connector\
WARNING: this bit is hard-wired in the HDL top to 0";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "transceiver output enable negative logic";
prefix = "oe_n";
description = "write 0: normal operation, the external sync pulse arrives to the FPGA and controls the macrocycle counter\
write 1: the external sync pulse is disabled; the macrocycle counting is based on internal counters";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "pulses counter reset";
prefix = "p_cnt_rst";
description = "resets the pulses counter";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "counting options";
prefix = "opt";
description = "0: external pulse resets the macrocycle counter whenever it arrives\
1: external pulse resets the macrocycle counter, only when it arrives in a window as expected by the\
processor and the macrocycle configuration. In this option for example if a macrocycle is set at 20 ms\
but a pulse arrives every 10 ms by mistake, then one every 2 pulses will be ignored.\
Note that the ext_sync_p_cnt will be counting in any case all the incoming pulses, so the error will\
be reported, but the macrocycle will run smoothly at 20 ms";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "safe window";
prefix = "safe_wind";
description = "0: processor busy with periodic traffic; reception of a new external pulse is NOT safe\
1: processor ready for a new external pulse; macrocycle periodic part has been played";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "ext sync pulses cnt";
prefix = "ext_sync_p_cnt";
field {
name = "ext_sync_p_cnt";
description = "number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;\
for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
----------------------------------------------------------------------------------------------------
-- SPEED CONFIG FROM THE FMC MEZZ --
----------------------------------------------------------------------------------------------------
reg {
name = "bus speed";
prefix = "speed";
field {
name = "WorldFIP speed, hard-wired on the FMC";
description = " 00: 31.25Kbps\
01: 1Mbps\
10: 2.5 Mbps\
11: 5 Mbps";
type = SLV;
size = 2;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
----------------------------------------------------------------------------------------------------
-- MACROCYCLE TURNAROUND SILENCE TIME COUNTERS --
----------------------------------------------------------------------------------------------------
reg {
name = "macrocycle lgth";
prefix = "macrocyc";
field {
name = "macrocycle lgth";
description = "duration of the macrocycle in number of 10ns-clk-ticks";
prefix = "lgth";
type = SLV;
size = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "macrocycle cnt start";
description = "write 1: initiates the counting of the macrocycle counter;\
the counter also automatically starts counting upon the arrival of an ext_sync pulse\
note: there is no need to clear the bit before writing another '1'";
prefix = "start";
type = MONOSTABLE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "macrocycle time cnt";
prefix = "macrocyc_time_cnt";
field {
name = "macrocycle time counter";
description = "current value of the macrocycle time counter;\
the counter top value is set through the register macrocycle lgth and it counts down;\
it is reloaded upon the activation of the macrocycle_cnt_start register bit OR automatically upon the arrival of an ext_sync pulse.";
type = SLV;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "macrocycles number cnt";
prefix = "macrocyc_num_cnt";
field {
name = "number of macrocycles";
description = "amount of macrocycles that have been counted since the application startup OR a rst_core;\
for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "turnaround lgth";
prefix = "turnar";
field {
name = "turnaround time";
description = "turnaround time (i.e. time to wait after reception/transmission of a frame and before transmitting a new frame) in number of 10ns-clk-ticks";
prefix = "lgth";
type = SLV;
size = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "turnaround cnt start";
description = "write 1: initiates the counting of the turnaround counter;\
the counter also automatically starts counting upon the end of a frame serialization (tx stop)\
OR upon the end of a frame deserialization (rx_frame_ok OR rx_frame_crc_error).\
note: there is no need to clear the bit before writing another '1'";
prefix = "start";
type = MONOSTABLE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "turnaround time cnt";
prefix = "turnar_time_cnt";
field {
name = "turnaround time counter";
description = "current value of the turnaround time counter;\
the counter top value is set through the register turnar_lgth and it counts down;\
it is reloaded upon the activation of the turnar_cnt_start OR automatically upon the end of a\
frame serialization (tx stop) OR upon the end of a frame deserialization (rx frame ok OR rx frame crc error).";
type = SLV;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "silence lgth";
prefix = "silen";
field {
name = "silence time";
description = "silence time (i.e. time that the masterFIP waits for a response frame) number of 10ns-clk-ticks";
prefix = "lgth";
type = SLV;
size = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "silence cnt start";
description = "initiates the counting of the silence counter;\
the counter also automatically starts counting upon the end of a frame serialization (tx stop)\
OR upon the end of a frame deserialization (rx frame ok OR rx frame crc error for the case of RP_FIN).\
note: there is no need to clear the bit before writing another '1'";
prefix = "start";
type = MONOSTABLE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "silence time cnt";
prefix = "silen_time_cnt";
field {
name = "silence time counter";
description = "current value of the silence time counter\
the counter top value is set through the register silen_lgth and it counts down;\
it is reloaded upon the activation of the silen_cnt_start OR automatically upon the end of a\
frame serialization (tx stop) OR upon the end of a frame deserialization (rx frame ok OR rx frame crc error for the case of RP_FIN).";
type = SLV;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
----------------------------------------------------------------------------------------------------
-- TX CTRL --
----------------------------------------------------------------------------------------------------
reg {
name = "tx ctrl";
prefix = "tx_ctrl";
field {
name = "tx rst";
description = "write 1: generates a 1-clk-tick-long reset to the serializer;\
note: there is no need to clear the bit before writing another '1'";
prefix = "rst";
type = MONOSTABLE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "tx strt";
description = "write 1: triggers the serializer to send a frame of tx_ctrl_bytes_num payload bytes;\
the bytes are retrieved one-by-one by the registers: tx_payld_ctrl, tx_payld_reg1..tx_payld_reg67;\
the bytes: FSS, CRC and FES are generated automatically by the serializer.\
note: there is no need to clear the bit before writing another '1'";
prefix = "start";
type = MONOSTABLE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "tx number of bytes";
description = "number of bytes to serialize; the number should include all the bytes in the Control and Data fields\
of a frame and not include the bytes in the Preamble(FSS), CRC, Postamble(FES) fields; the fmc_masterFIP_core\
samples this number upon the tx_strt; note that for the max supported WorldFIP frame, which is a message of\
256 Data bytes, the number of bytes to serialize = 263 (Control byte+6 address bytes+256 Data bytes)";
prefix = "bytes_num";
type = SLV;
size = 16; -- under normal conditions the value should be max 262
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
----------------------------------------------------------------------------------------------------
-- TX STATUS --
----------------------------------------------------------------------------------------------------
reg {
name = "tx status";
prefix = "tx_stat";
field {
name = "tx ended";
description = "indication that the serializer finished the delivery of a frame;\
the bit stays active until a rst_core OR a tx_ctrl_rst OR a tx_ctrl_strt";
prefix = "stop";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "tx enable";
description = "FielDrive fd_txena signal;\
read 0: masterFIP serializer is inactive\
read 1: masterFIP serializer is active transmitting bits on the bus";
prefix = "ena";
type = BIT;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "tx status current byte index";
description = "index of the current byte being serialized;\
the counting starts from 0 after the Preamble(FSS) (index 0 is for the Control byte)\
and counts up to 262 for the max frame (counting stops before the CRC bytes)";
prefix = "curr_byte_indx";
type = SLV;
align = 8;
size = 16; -- under normal conditions the value should be max 262
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
----------------------------------------------------------------------------------------------------
-- FielDrive TXER, WDGN, CDN --
----------------------------------------------------------------------------------------------------
reg {
name = "FielDrive wdgn, cdn";
prefix = "fd";
field {
name = "FielDrive watchdog";
description = "read 1: the fd_wdgn is active which means that a transmission >1024 bytes-long has been detected\
read 0: no problemo\
Note that the fd_wdgn stays active until a FielDrive reset rst_fd";
prefix = "wdg";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FielDrive carrier detect";
description = "read 1: carrier detect active\
read 0: no bus traffic";
prefix = "cd";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "FielDrive wdg timestamp";
prefix = "fd_wdg_tstamp";
field {
name = "fd_wdgn_tstamp";
description = "timestamp of the moment in the macrocycle (macrocycle_cnt) when the fd_wdg activation (rising edge) was detected.\
The field is automatically cleared upon a rst_fd OR rst_core";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "FielDrive txer cnt";
prefix = "fd_txer_cnt";
field {
name = "fd_txer_cnt";
description = "counter of the number of fd_txer rising edges that appear in the current macrocycle.\
The field is automatically cleared upon a new macrocycle OR upon a rst_fd OR rst_core.\
Note that a fd_txer indicates underload/overload of the bus (like for example when the\
WorldFIP cable has been disconnected) OR transmission without a Manchester-edge-detection after the duration of 4 bits.\
Upon cable disconnection, we have noticed at least 1 fd_txer per transmitted frame.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "FielDrive txer tstamp";
prefix = "fd_txer_tstamp";
field {
name = "fd_txer_tstamp";
description = "timestamp of the last moment in the macrocycle when the fd_txer was activated.\
The field is automatically cleared upon a new macrocycle OR upon a rst_fd OR rst_core";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
----------------------------------------------------------------------------------------------------
-- RX CTRL --
----------------------------------------------------------------------------------------------------
reg {
name = "rx ctrl";
prefix = "rx_ctrl";
description = "active high reset of the deserializer";
field {
name = "rx rst";
description = "write 1: generates a 1-clk-tick-long reset to the deserializer\
note: there is no need to clear the bit before writing another '1'\
note: the deserializer is automatically hw-reset when the serializer is active.";
prefix = "rst";
type = MONOSTABLE;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
----------------------------------------------------------------------------------------------------
-- RX STATUS --
----------------------------------------------------------------------------------------------------
reg {
name = "rx status";
prefix = "rx_stat";
field {
name = "rx Preamble(FSS) detected";
description = "indication that the deserializer has detected a Preamble(FSS);\
the bit stays active until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core)";
prefix = "pream_ok";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "rx CTRL byte detected";
description = "indication that the deserializer has received the CTRL byte, i.e. the first byte after a Preamble(FSS);\
the bit stays active until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).\
Note that the content of the byte is not checked against acceptable CTRL byte codes";
prefix = "ctrl_byte_ok";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "rx frame ok";
description = "indication that the deserializer has finished with the reception of a complete frame;\
the Preamble(FSS), CRC and Postambe(FES) of the frame are all ok.\
The bit stays high until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).\
Upon the activation of the rx_frame_ok the processor should read the bytes_num register\
and then the corresponding amount of rx_payld_regs. The content of these registers remains stable\
until a reset of the deserializer OR a new rx_frame_ok; this is at minimum 23.2 us (i.e. (min node turnaround timee = 4 us) + (RP_FIN duration = 19.2 us)).";
prefix = "frame_ok";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "rx frame crc error";
description = "indication that the deserializer has detected a frame with CRC error;\
The bit stays high until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).";
prefix = "frame_crc_err";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "rx bytes number error";
description = "indication that the deserializer has counted the reception of more than 266 bytes;\
The bit stays high until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).";
prefix = "bytes_num_err";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "rx number of payload bytes";
description = "number of payload bytes that have been received by the deserializer upon the rx_frame_ok activation.\
The counter includes all the bytes that come after the Control byte and before the CRC bytes.\
note that for the max WorldFIP frame size, the number of payload bytes = 262 bytes (without Preamble, Control, CRC, Postamble).\
The register keeps its value until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).";
prefix = "bytes_num";
type = SLV;
size = 16; -- under normal conditions the value should be max 262
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx current word index";
prefix = "rx_stat_curr_word_indx";
field {
name = "current word index";
description = "index of the current 32-bit-word being deserialized;\
Note that in word 1: LSB is the Control byte; the other 3 bytes are to be ignored\
then word 2: contains the first 4 payload bytes..etc\
The max frame size is 67 words (including the word for the Control byte).\
The last word may also include CRC bytes; for that, upon the rx_frame_ok,\
the rx_bytes_num indicates the exact number of payload bytes to be read;\
The register keeps its value until a reset of the deserializer (this takes place automatically upon the activation of the serializer,\
OR upon a rx_ctrl_rst OR upon a rst_core).";
type = SLV;
size = 8; -- under normal conditions the value should be max 67
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx num of frames with CRC error";
prefix = "rx_stat_crc_err_cnt";
field {
name = "rx number of frames with CRC error";
description = "number of frames with CRC error since the application startup OR a rst_core";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
----------------------------------------------------------------------------------------------------
-- RX FRAME PAYLOAD --
----------------------------------------------------------------------------------------------------
reg {
name = "rx payload ctrl byte";
prefix = "rx_payld_ctrl";
description = "contains the 8-bits of the control field of a received frame";
field {
name = "rx payload ctrl byte";
description = "contains the 8-bits of the control field of a received frame";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg1";
prefix = "rx_payld_reg1";
description = "32 bits of the received frame";
field {
name = "reg 1";
description = "1st 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg2";
prefix = "rx_payld_reg2";
description = "32 bits of the received frame";
field {
name = "reg2";
description = "2nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg3";
prefix = "rx_payld_reg3";
description = "32 bits of the received frame";
field {
name = "reg3";
description = "3rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg4";
prefix = "rx_payld_reg4";
description = "32 bits of the received frame";
field {
name = "reg4";
description = "4th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg5";
prefix = "rx_payld_reg5";
description = "32 bits of the received frame";
field {
name = "reg5";
description = "5th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg6";
prefix = "rx_payld_reg6";
description = "32 bits of the received frame";
field {
name = "reg6";
description = "6th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg7";
prefix = "rx_payld_reg7";
description = "32 bits of the received frame";
field {
name = "reg7";
description = "7th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg8";
prefix = "rx_payld_reg8";
description = "32 bits of the received frame";
field {
name = "reg8";
description = "8th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg9";
prefix = "rx_payld_reg9";
description = "32 bits of the received frame";
field {
name = "reg9";
description = "9th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg10";
prefix = "rx_payld_reg10";
description = "32 bits of the received frame";
field {
name = "reg10";
description = "10th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg11";
prefix = "rx_payld_reg11";
description = "32 bits of the received frame";
field {
name = "reg11";
description = "11th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg12";
prefix = "rx_payld_reg12";
description = "32 bits of the received frame";
field {
name = "reg12";
description = "12th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg13";
prefix = "rx_payld_reg13";
description = "32 bits of the received frame";
field {
name = "reg13";
description = "13th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg14";
prefix = "rx_payld_reg14";
description = "32 bits of the received frame";
field {
name = "reg14";
description = "14th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg15";
prefix = "rx_payld_reg15";
description = "32 bits of the received frame";
field {
name = "reg15";
description = "15th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg16";
prefix = "rx_payld_reg16";
description = "32 bits of the received frame";
field {
name = "reg16";
description = "16th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg17";
prefix = "rx_payld_reg17";
description = "32 bits of the received frame";
field {
name = "reg17";
description = "17th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg18";
prefix = "rx_payld_reg18";
description = "32 bits of the received frame";
field {
name = "reg18";
description = "18th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg19";
prefix = "rx_payld_reg19";
description = "32 bits of the received frame";
field {
name = "reg19";
description = "19th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg20";
prefix = "rx_payld_reg20";
description = "32 bits of the received frame";
field {
name = "reg20";
description = "20th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg21";
prefix = "rx_payld_reg21";
description = "32 bits of the received frame";
field {
name = "reg21";
description = "21th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg22";
prefix = "rx_payld_reg22";
description = "32 bits of the received frame";
field {
name = "reg22";
description = "22th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg23";
prefix = "rx_payld_reg23";
description = "32 bits of the received frame";
field {
name = "reg23";
description = "23th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg24";
prefix = "rx_payld_reg24";
description = "32 bits of the received frame";
field {
name = "reg24";
description = "24th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg25";
prefix = "rx_payld_reg25";
description = "32 bits of the received frame";
field {
name = "reg25";
description = "25th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg26";
prefix = "rx_payld_reg26";
description = "32 bits of the received frame";
field {
name = "reg26";
description = "26th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg27";
prefix = "rx_payld_reg27";
description = "32 bits of the received frame";
field {
name = "reg27";
description = "27th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg28";
prefix = "rx_payld_reg28";
description = "32 bits of the received frame";
field {
name = "reg28";
description = "28th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg29";
prefix = "rx_payld_reg29";
description = "32 bits of the received frame";
field {
name = "reg29";
description = "29th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg30";
prefix = "rx_payld_reg30";
description = "32 bits of the received frame";
field {
name = "reg30";
description = "30th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg31";
prefix = "rx_payld_reg31";
description = "32 bits of the received frame";
field {
name = "reg31";
description = "31th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg32";
prefix = "rx_payld_reg32";
description = "32 bits of the received frame";
field {
name = "reg32";
description = "32th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg33";
prefix = "rx_payld_reg33";
description = "32 bits of the received frame";
field {
name = "reg 33";
description = "33rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg34";
prefix = "rx_payld_reg34";
description = "32 bits of the received frame";
field {
name = "reg34";
description = "34th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg35";
prefix = "rx_payld_reg35";
description = "32 bits of the received frame";
field {
name = "reg35";
description = "35th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg36";
prefix = "rx_payld_reg36";
description = "32 bits of the received frame";
field {
name = "reg36";
description = "36th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg37";
prefix = "rx_payld_reg37";
description = "32 bits of the received frame";
field {
name = "reg37";
description = "37th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg38";
prefix = "rx_payld_reg38";
description = "32 bits of the received frame";
field {
name = "reg38";
description = "38th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg39";
prefix = "rx_payld_reg39";
description = "32 bits of the received frame";
field {
name = "reg39";
description = "39th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg40";
prefix = "rx_payld_reg40";
description = "32 bits of the received frame";
field {
name = "reg40";
description = "40th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg41";
prefix = "rx_payld_reg41";
description = "32 bits of the received frame";
field {
name = "reg41";
description = "41th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg42";
prefix = "rx_payld_reg42";
description = "32 bits of the received frame";
field {
name = "reg42";
description = "42nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg43";
prefix = "rx_payld_reg43";
description = "32 bits of the received frame";
field {
name = "reg43";
description = "43rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg44";
prefix = "rx_payld_reg44";
description = "32 bits of the received frame";
field {
name = "reg44";
description = "44th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg45";
prefix = "rx_payld_reg45";
description = "32 bits of the received frame";
field {
name = "reg45";
description = "45th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg46";
prefix = "rx_payld_reg46";
description = "32 bits of the received frame";
field {
name = "reg46";
description = "46th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg47";
prefix = "rx_payld_reg47";
description = "32 bits of the received frame";
field {
name = "reg47";
description = "47th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg48";
prefix = "rx_payld_reg48";
description = "32 bits of the received frame";
field {
name = "reg48";
description = "48th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg49";
prefix = "rx_payld_reg49";
description = "32 bits of the received frame";
field {
name = "reg49";
description = "49th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg50";
prefix = "rx_payld_reg50";
description = "32 bits of the received frame";
field {
name = "reg50";
description = "50th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg51";
prefix = "rx_payld_reg51";
description = "32 bits of the received frame";
field {
name = "reg51";
description = "51st 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg52";
prefix = "rx_payld_reg52";
description = "32 bits of the received frame";
field {
name = "reg52";
description = "52nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg53";
prefix = "rx_payld_reg53";
description = "32 bits of the received frame";
field {
name = "reg53";
description = "53rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg54";
prefix = "rx_payld_reg54";
description = "32 bits of the received frame";
field {
name = "reg54";
description = "54th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg55";
prefix = "rx_payld_reg55";
description = "32 bits of the received frame";
field {
name = "reg55";
description = "55th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg56";
prefix = "rx_payld_reg56";
description = "32 bits of the received frame";
field {
name = "reg56";
description = "56th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg57";
prefix = "rx_payld_reg57";
description = "32 bits of the received frame";
field {
name = "reg57";
description = "57th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg58";
prefix = "rx_payld_reg58";
description = "32 bits of the received frame";
field {
name = "reg58";
description = "58th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg59";
prefix = "rx_payld_reg59";
description = "32 bits of the received frame";
field {
name = "reg59";
description = "59th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg60";
prefix = "rx_payld_reg60";
description = "32 bits of the received frame";
field {
name = "reg60";
description = "60th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg61";
prefix = "rx_payld_reg61";
description = "32 bits of the received frame";
field {
name = "reg61";
description = "61st 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg62";
prefix = "rx_payld_reg62";
description = "32 bits of the received frame";
field {
name = "reg62";
description = "62nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg63";
prefix = "rx_payld_reg63";
description = "32 bits of the received frame";
field {
name = "reg63";
description = "63rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg64";
prefix = "rx_payld_reg64";
description = "32 bits of the received frame";
field {
name = "reg64";
description = "64th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg65";
prefix = "rx_payld_reg65";
description = "32 bits of the received frame";
field {
name = "reg65";
description = "65th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg66";
prefix = "rx_payld_reg66";
description = "32 bits of the received frame";
field {
name = "reg66";
description = "66th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "rx payload reg67";
prefix = "rx_payld_reg67";
description = "32 bits of the received frame";
field {
name = "reg67";
description = "67th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
----------------------------------------------------------------------------------------------------
-- TX FRAME PAYLOAD --
----------------------------------------------------------------------------------------------------
reg {
name = "tx ctrl byte";
prefix = "tx_payld_ctrl";
description = "contains the 8-bits of the control field of a frame to transmit";
field {
name = "tx ctrl byte";
description = "contains the 8-bits of the control field of a frame to transmit";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg1";
prefix = "tx_payld_reg1";
description = "32 bits of the received frame";
field {
name = "reg1";
description = "1st 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg2";
prefix = "tx_payld_reg2";
description = "32 bits of the received frame";
field {
name = "reg2";
description = "2nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg3";
prefix = "tx_payld_reg3";
description = "32 bits of the received frame";
field {
name = "reg3";
description = "3rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg4";
prefix = "tx_payld_reg4";
description = "32 bits of the received frame";
field {
name = "reg4";
description = "4th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg5";
prefix = "tx_payld_reg5";
description = "32 bits of the received frame";
field {
name = "reg5";
description = "5th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg6";
prefix = "tx_payld_reg6";
description = "32 bits of the received frame";
field {
name = "reg6";
description = "6th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg7";
prefix = "tx_payld_reg7";
description = "32 bits of the received frame";
field {
name = "reg7";
description = "7th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg8";
prefix = "tx_payld_reg8";
description = "32 bits of the received frame";
field {
name = "reg8";
description = "8th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg9";
prefix = "tx_payld_reg9";
description = "32 bits of the received frame";
field {
name = "reg9";
description = "9th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg10";
prefix = "tx_payld_reg10";
description = "32 bits of the received frame";
field {
name = "reg10";
description = "10th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg11";
prefix = "tx_payld_reg11";
description = "32 bits of the received frame";
field {
name = "reg11";
description = "11th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg12";
prefix = "tx_payld_reg12";
description = "32 bits of the received frame";
field {
name = "reg12";
description = "12th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg13";
prefix = "tx_payld_reg13";
description = "32 bits of the received frame";
field {
name = "reg13";
description = "13th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg14";
prefix = "tx_payld_reg14";
description = "32 bits of the received frame";
field {
name = "reg14";
description = "14th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg15";
prefix = "tx_payld_reg15";
description = "32 bits of the received frame";
field {
name = "reg15";
description = "15th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg16";
prefix = "tx_payld_reg16";
description = "32 bits of the received frame";
field {
name = "reg16";
description = "16th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg17";
prefix = "tx_payld_reg17";
description = "32 bits of the received frame";
field {
name = "reg17";
description = "17th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg18";
prefix = "tx_payld_reg18";
description = "32 bits of the received frame";
field {
name = "reg18";
description = "18th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg19";
prefix = "tx_payld_reg19";
description = "32 bits of the received frame";
field {
name = "reg19";
description = "19th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg20";
prefix = "tx_payld_reg20";
description = "32 bits of the received frame";
field {
name = "reg20";
description = "20th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg21";
prefix = "tx_payld_reg21";
description = "32 bits of the received frame";
field {
name = "reg21";
description = "21th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg22";
prefix = "tx_payld_reg22";
description = "32 bits of the received frame";
field {
name = "reg22";
description = "22th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg23";
prefix = "tx_payld_reg23";
description = "32 bits of the received frame";
field {
name = "reg23";
description = "23th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg24";
prefix = "tx_payld_reg24";
description = "32 bits of the received frame";
field {
name = "reg24";
description = "24th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg25";
prefix = "tx_payld_reg25";
description = "32 bits of the received frame";
field {
name = "reg25";
description = "25th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg26";
prefix = "tx_payld_reg26";
description = "32 bits of the received frame";
field {
name = "reg26";
description = "26th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg27";
prefix = "tx_payld_reg27";
description = "32 bits of the received frame";
field {
name = "reg27";
description = "27th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg28";
prefix = "tx_payld_reg28";
description = "32 bits of the received frame";
field {
name = "reg28";
description = "28th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg29";
prefix = "tx_payld_reg29";
description = "32 bits of the received frame";
field {
name = "reg29";
description = "29th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg30";
prefix = "tx_payld_reg30";
description = "32 bits of the received frame";
field {
name = "reg30";
description = "30th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg31";
prefix = "tx_payld_reg31";
description = "32 bits of the received frame";
field {
name = "reg31";
description = "31th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg32";
prefix = "tx_payld_reg32";
description = "32 bits of the received frame";
field {
name = "reg32";
description = "32th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg33";
prefix = "tx_payld_reg33";
description = "32 bits of the received frame";
field {
name = "reg 33";
description = "33rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg34";
prefix = "tx_payld_reg34";
description = "32 bits of the received frame";
field {
name = "reg34";
description = "34th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg35";
prefix = "tx_payld_reg35";
description = "32 bits of the received frame";
field {
name = "reg35";
description = "35th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg36";
prefix = "tx_payld_reg36";
description = "32 bits of the received frame";
field {
name = "reg36";
description = "36th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg37";
prefix = "tx_payld_reg37";
description = "32 bits of the received frame";
field {
name = "reg37";
description = "37th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg38";
prefix = "tx_payld_reg38";
description = "32 bits of the received frame";
field {
name = "reg38";
description = "38th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg39";
prefix = "tx_payld_reg39";
description = "32 bits of the received frame";
field {
name = "reg39";
description = "39th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg40";
prefix = "tx_payld_reg40";
description = "32 bits of the received frame";
field {
name = "reg40";
description = "40th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg41";
prefix = "tx_payld_reg41";
description = "32 bits of the received frame";
field {
name = "reg41";
description = "41th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg42";
prefix = "tx_payld_reg42";
description = "32 bits of the received frame";
field {
name = "reg42";
description = "42nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg43";
prefix = "tx_payld_reg43";
description = "32 bits of the received frame";
field {
name = "reg43";
description = "43rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg44";
prefix = "tx_payld_reg44";
description = "32 bits of the received frame";
field {
name = "reg44";
description = "44th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg45";
prefix = "tx_payld_reg45";
description = "32 bits of the received frame";
field {
name = "reg45";
description = "45th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg46";
prefix = "tx_payld_reg46";
description = "32 bits of the received frame";
field {
name = "reg46";
description = "46th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg47";
prefix = "tx_payld_reg47";
description = "32 bits of the received frame";
field {
name = "reg47";
description = "47th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg48";
prefix = "tx_payld_reg48";
description = "32 bits of the received frame";
field {
name = "reg48";
description = "48th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg49";
prefix = "tx_payld_reg49";
description = "32 bits of the received frame";
field {
name = "reg49";
description = "49th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg50";
prefix = "tx_payld_reg50";
description = "32 bits of the received frame";
field {
name = "reg50";
description = "50th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg51";
prefix = "tx_payld_reg51";
description = "32 bits of the received frame";
field {
name = "reg51";
description = "51st 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg52";
prefix = "tx_payld_reg52";
description = "32 bits of the received frame";
field {
name = "reg52";
description = "52nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg53";
prefix = "tx_payld_reg53";
description = "32 bits of the received frame";
field {
name = "reg53";
description = "53rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg54";
prefix = "tx_payld_reg54";
description = "32 bits of the received frame";
field {
name = "reg54";
description = "54th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg55";
prefix = "tx_payld_reg55";
description = "32 bits of the received frame";
field {
name = "reg55";
description = "55th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg56";
prefix = "tx_payld_reg56";
description = "32 bits of the received frame";
field {
name = "reg56";
description = "56th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg57";
prefix = "tx_payld_reg57";
description = "32 bits of the received frame";
field {
name = "reg57";
description = "57th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg58";
prefix = "tx_payld_reg58";
description = "32 bits of the received frame";
field {
name = "reg58";
description = "58th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg59";
prefix = "tx_payld_reg59";
description = "32 bits of the received frame";
field {
name = "reg59";
description = "59th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg60";
prefix = "tx_payld_reg60";
description = "32 bits of the received frame";
field {
name = "reg60";
description = "60th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg61";
prefix = "tx_payld_reg61";
description = "32 bits of the received frame";
field {
name = "reg61";
description = "61st 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg62";
prefix = "tx_payld_reg62";
description = "32 bits of the received frame";
field {
name = "reg62";
description = "62nd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg63";
prefix = "tx_payld_reg63";
description = "32 bits of the received frame";
field {
name = "reg63";
description = "63rd 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg64";
prefix = "tx_payld_reg64";
description = "32 bits of the received frame";
field {
name = "reg64";
description = "64th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg65";
prefix = "tx_payld_reg65";
description = "32 bits of the received frame";
field {
name = "reg65";
description = "65th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg66";
prefix = "tx_payld_reg66";
description = "32 bits of the received frame";
field {
name = "reg66";
description = "66th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "tx payload reg67";
prefix = "tx_payld_reg67";
description = "32 bits of the received frame";
field {
name = "reg67";
description = "67th 32-bit word";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
}; masterfip-gw-adam-proposed_master/rtl/wbgen/masterfip_wbgen2_csr.h 0000664 0000000 0000000 00000071400 13422611646 0025757 0 ustar 00root root 0000000 0000000 /*
Register definitions for slave core: FMC masterFIP core registers
* File : masterfip_wbgen2_csr.h
* Author : auto-generated by wbgen2 from masterfip_csr.wb
* Created : 07/17/17 17:07:35
* Version : 0x00020000
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_MASTERFIP_CSR_WB
#define __WBGEN2_REGDEFS_MASTERFIP_CSR_WB
#ifdef __KERNEL__
#include
#else
#include
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<