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bpm
bpm-sw
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b1547a32
Commit
b1547a32
authored
Aug 17, 2016
by
Lucas Russo
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include/hw/*: update acq core register file
github lnls-dig/bpm-gw@6a66271665 changed it, so we updated it here.
parent
59ca297f
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wb_acq_core_regs.h
include/hw/wb_acq_core_regs.h
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include/hw/wb_acq_core_regs.h
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b1547a32
...
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@@ -3,7 +3,7 @@
* File : wb_acq_core_regs.h
* Author : auto-generated by wbgen2 from acq_core.wb
* Created :
Thu Oct 22 17:24:54 2015
* Created :
Wed Aug 17 12:04:55 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE acq_core.wb
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@@ -109,16 +109,16 @@
#define ACQ_CORE_TRIG_CFG_SW_TRIG_EN WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Channel selection for internal trigger in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_MASK WBGEN2_GEN_MASK(4,
2
)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_MASK WBGEN2_GEN_MASK(4,
5
)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_SHIFT 4
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 4,
2
)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 4,
2
)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 4,
5
)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 4,
5
)
/* definitions for field: Reserved in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_RESERVED_MASK WBGEN2_GEN_MASK(
6, 26
)
#define ACQ_CORE_TRIG_CFG_RESERVED_SHIFT
6
#define ACQ_CORE_TRIG_CFG_RESERVED_W(value) WBGEN2_GEN_WRITE(value,
6, 26
)
#define ACQ_CORE_TRIG_CFG_RESERVED_R(reg) WBGEN2_GEN_READ(reg,
6, 26
)
#define ACQ_CORE_TRIG_CFG_RESERVED_MASK WBGEN2_GEN_MASK(
9, 23
)
#define ACQ_CORE_TRIG_CFG_RESERVED_SHIFT
9
#define ACQ_CORE_TRIG_CFG_RESERVED_W(value) WBGEN2_GEN_WRITE(value,
9, 23
)
#define ACQ_CORE_TRIG_CFG_RESERVED_R(reg) WBGEN2_GEN_READ(reg,
9, 23
)
/* definitions for register: Trigger data config threshold */
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