sm_io/chips/*: use new SMPR API for pluggable operations

Now, we pass the pointer to the operation we want to use it, instead of the enum.

sm_io/chips/*: use new SMPR API for pluggable operations
Now, we pass the pointer to the operation we want to use it, instead of the enum.
8fa46d2a · Lucas Russo · ad4d4456 · 8fa46d2a · 8fa46d2a · 8fa46d2a
Commit 8fa46d2a authored Aug 03, 2016 by Lucas Russo
6 changed files
--- a/src/sm_io/chips/sm_ch_24aa64.c
+++ b/src/sm_io/chips/sm_ch_24aa64.c
@@ -62,7 +62,7 @@ smch_24aa64_t * smch_24aa64_new (smio_t *parent, uint64_t base, uint32_t addr,
    smch_24aa64_t *self = (smch_24aa64_t *) zmalloc (sizeof *self);
    ASSERT_ALLOC(self, err_self_alloc);

-    self->i2c = smpr_new (SMCH_24AA64_NAME, parent, SMPR_I2C, verbose);
+    self->i2c = smpr_new (SMCH_24AA64_NAME, parent, &smpr_proto_ops_i2c, verbose);
    ASSERT_ALLOC(self->i2c, err_i2c_alloc);

    /* Initalize the I2C protocol */

--- a/src/sm_io/chips/sm_ch_ad9510.c
+++ b/src/sm_io/chips/sm_ch_ad9510.c
@@ -65,7 +65,7 @@ smch_ad9510_t * smch_ad9510_new (smio_t *parent, uint64_t base, uint32_t ss,
    smch_ad9510_t *self = (smch_ad9510_t *) zmalloc (sizeof *self);
    ASSERT_ALLOC(self, err_self_alloc);

-    self->spi = smpr_new (SMCH_AD9510_NAME, parent, SMPR_SPI, verbose);
+    self->spi = smpr_new (SMCH_AD9510_NAME, parent, &smpr_proto_ops_spi, verbose);
    ASSERT_ALLOC(self->spi, err_spi_alloc);

    /* Initalize the SPI protocol */
@@ -735,7 +735,7 @@ static smch_err_e _smch_ad9510_init (smch_ad9510_t *self)
            err_smpr_write, SMCH_ERR_RW_SMPR);

    /* According to AD9510 datasheet Rev. B, page 46, table 25, regester 0x00 (CFG_SERIAL),
-     * does not need to be updated by setting the "update registers" bit. We still wait our default 
+     * does not need to be updated by setting the "update registers" bit. We still wait our default
     * ammount of time to be sure the chip is indeed reset */
    SMCH_AD9510_WAIT_DFLT;

@@ -746,7 +746,7 @@ static smch_err_e _smch_ad9510_init (smch_ad9510_t *self)
            err_smpr_write, SMCH_ERR_RW_SMPR);

    /* According to AD9510 datasheet Rev. B, page 46, table 25, regester 0x00 (CFG_SERIAL),
-     * does not need to be updated by setting the "update registers" bit. We still wait our default 
+     * does not need to be updated by setting the "update registers" bit. We still wait our default
     * ammount of time to be sure the chip is indeed reset */

    /* Wait for reset to complete */

--- a/src/sm_io/chips/sm_ch_isla216p.c
+++ b/src/sm_io/chips/sm_ch_isla216p.c
@@ -58,7 +58,7 @@ smch_isla216p_t * smch_isla216p_new (smio_t *parent, uint64_t base, uint32_t ss,
    smch_isla216p_t *self = (smch_isla216p_t *) zmalloc (sizeof *self);
    ASSERT_ALLOC(self, err_self_alloc);

-    self->spi = smpr_new (SMCH_ISLA216P_NAME, parent, SMPR_SPI, verbose);
+    self->spi = smpr_new (SMCH_ISLA216P_NAME, parent, &smpr_proto_ops_spi, verbose);
    ASSERT_ALLOC(self->spi, err_spi_alloc);

    /* Initalize the SPI protocol */
@@ -199,7 +199,7 @@ static smch_err_e _smch_isla216p_init (smch_isla216p_t *self)
            err_smpr_write, SMCH_ERR_RW_SMPR);
 #endif

-    data = ISLA216P_NAPSLP_W(ISLA216P_NAPSLP_NORMAL_OPERATION); 
+    data = ISLA216P_NAPSLP_W(ISLA216P_NAPSLP_NORMAL_OPERATION);
    rw_err = _smch_isla216p_write_8 (self, ISLA216P_REG_NAPSLP, &data);
    ASSERT_TEST(rw_err == sizeof(uint8_t), "Could not write to ISLA216P_REG_NAPSLP",
            err_smpr_write, SMCH_ERR_RW_SMPR);

--- a/src/sm_io/chips/sm_ch_pca9547.c
+++ b/src/sm_io/chips/sm_ch_pca9547.c
@@ -52,7 +52,7 @@ smch_pca9547_t * smch_pca9547_new (smio_t *parent, uint64_t base, uint32_t addr,
    smch_pca9547_t *self = (smch_pca9547_t *) zmalloc (sizeof *self);
    ASSERT_ALLOC(self, err_self_alloc);

-    self->i2c = smpr_new (SMCH_PCA9547_NAME, parent, SMPR_I2C, verbose);
+    self->i2c = smpr_new (SMCH_PCA9547_NAME, parent, &smpr_proto_ops_i2c, verbose);
    ASSERT_ALLOC(self->i2c, err_i2c_alloc);

    /* Initalize the I2C protocol */

--- a/src/sm_io/chips/sm_ch_rffe.c
+++ b/src/sm_io/chips/sm_ch_rffe.c
@@ -54,7 +54,7 @@ smch_rffe_t * smch_rffe_new (smio_t *parent, int verbose)
    smch_rffe_t *self = (smch_rffe_t *) zmalloc (sizeof *self);
    ASSERT_ALLOC(self, err_self_alloc);

-    self->bsmp = smpr_new (SMCH_RFFE_NAME, parent, SMPR_BSMP, verbose);
+    self->bsmp = smpr_new (SMCH_RFFE_NAME, parent, &smpr_proto_ops_bsmp, verbose);
    ASSERT_ALLOC(self->bsmp, err_bsmp_alloc);

    /* Initalize the BSMP protocol */

--- a/src/sm_io/chips/sm_ch_si57x.c
+++ b/src/sm_io/chips/sm_ch_si57x.c
@@ -85,7 +85,7 @@ smch_si57x_t * smch_si57x_new (smio_t *parent, uint64_t base, uint32_t addr,
    smch_si57x_t *self = (smch_si57x_t *) zmalloc (sizeof *self);
    ASSERT_ALLOC(self, err_self_alloc);

-    self->i2c = smpr_new (SMCH_SI57X_NAME, parent, SMPR_I2C, verbose);
+    self->i2c = smpr_new (SMCH_SI57X_NAME, parent, &smpr_proto_ops_i2c, verbose);
    ASSERT_ALLOC(self->i2c, err_i2c_alloc);

    /* Initalize the I2C protocol */