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bpm-sw
Commit 1acccbcb authored by Lucas Russo's avatar Lucas Russo
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sm_io/modules/*: remove hardcoded offsets as they are read from SDB 

These addresses are not needed anymore,
as they are already read from SDB and passed
to the SMIO as part of the base address.
parent 60caf8f1
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Inline Side-by-side
Showing with 97 additions and 97 deletions
src/sm_io/modules/acq/sm_io_acq_exp.c
View file @ 1acccbcb
......@@ -673,7 +673,7 @@ err_inv_skip_trig:
#define ACQ_HW_DATA_TRIG_POL_MIN 0 /* positive slope: 0 -> 1 */
#define ACQ_HW_DATA_TRIG_POL_MAX 1 /* negative slope: 1 -> 0 */
RW_PARAM_FUNC(acq, hw_data_trig_pol) {
SET_GET_PARAM(acq, WB_ACQ_CORE_CTRL_REGS_OFFS, ACQ_CORE, TRIG_CFG,
SET_GET_PARAM(acq, 0x0, ACQ_CORE, TRIG_CFG,
HW_TRIG_POL, SINGLE_BIT_PARAM, ACQ_HW_DATA_TRIG_POL_MIN,
ACQ_HW_DATA_TRIG_POL_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -681,7 +681,7 @@ RW_PARAM_FUNC(acq, hw_data_trig_pol) {
#define ACQ_HW_DATA_TRIG_SEL_MIN 0
#define ACQ_HW_DATA_TRIG_SEL_MAX 3
RW_PARAM_FUNC(acq, hw_data_trig_sel) {
SET_GET_PARAM(acq, WB_ACQ_CORE_CTRL_REGS_OFFS, ACQ_CORE, TRIG_CFG,
SET_GET_PARAM(acq, 0x0, ACQ_CORE, TRIG_CFG,
INT_TRIG_SEL, MULT_BIT_PARAM, ACQ_HW_DATA_TRIG_SEL_MIN,
ACQ_HW_DATA_TRIG_SEL_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -689,7 +689,7 @@ RW_PARAM_FUNC(acq, hw_data_trig_sel) {
#define ACQ_HW_DATA_TRIG_FILT_MIN 0
#define ACQ_HW_DATA_TRIG_FILT_MAX ((1 << 8)-1)
RW_PARAM_FUNC(acq, hw_data_trig_filt) {
SET_GET_PARAM(acq, WB_ACQ_CORE_CTRL_REGS_OFFS, ACQ_CORE, TRIG_DATA_CFG,
SET_GET_PARAM(acq, 0x0, ACQ_CORE, TRIG_DATA_CFG,
THRES_FILT, MULT_BIT_PARAM, ACQ_HW_DATA_TRIG_FILT_MIN,
ACQ_HW_DATA_TRIG_FILT_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -698,7 +698,7 @@ RW_PARAM_FUNC(acq, hw_data_trig_filt) {
#define ACQ_CORE_TRIG_DATA_THRES_W(val) (val)
#define ACQ_CORE_TRIG_DATA_THRES_MASK ((1ULL<<32)-1)
RW_PARAM_FUNC(acq, hw_data_trig_thres) {
SET_GET_PARAM(acq, WB_ACQ_CORE_CTRL_REGS_OFFS, ACQ_CORE, TRIG_DATA_THRES,
SET_GET_PARAM(acq, 0x0, ACQ_CORE, TRIG_DATA_THRES,
/* No field */, MULT_BIT_PARAM, /* No minimum check*/,
/* No maximum check */, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -708,7 +708,7 @@ RW_PARAM_FUNC(acq, hw_data_trig_thres) {
#define ACQ_CORE_TRIG_DLY_W(val) (val)
#define ACQ_CORE_TRIG_DLY_MASK ((1ULL<<32)-1)
RW_PARAM_FUNC(acq, hw_trig_dly) {
SET_GET_PARAM(acq, WB_ACQ_CORE_CTRL_REGS_OFFS, ACQ_CORE, TRIG_DLY,
SET_GET_PARAM(acq, 0x0, ACQ_CORE, TRIG_DLY,
/* No field*/, MULT_BIT_PARAM, /* No minimum check */,
/* No maximum check */, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -719,7 +719,7 @@ RW_PARAM_FUNC(acq, hw_trig_dly) {
#define ACQ_SW_TRIG_MIN 0
#define ACQ_SW_TRIG_MAX 1
RW_PARAM_FUNC(acq, sw_trig) {
SET_GET_PARAM(acq, WB_ACQ_CORE_CTRL_REGS_OFFS, ACQ_CORE, SW_TRIG,
SET_GET_PARAM(acq, 0x0, ACQ_CORE, SW_TRIG,
/* No field*/, MULT_BIT_PARAM, ACQ_SW_TRIG_MIN,
ACQ_SW_TRIG_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -727,7 +727,7 @@ RW_PARAM_FUNC(acq, sw_trig) {
#define ACQ_FSM_STOP_MIN 0
#define ACQ_FSM_STOP_MAX 1
RW_PARAM_FUNC(acq, fsm_stop) {
SET_GET_PARAM(acq, WB_ACQ_CORE_CTRL_REGS_OFFS, ACQ_CORE, CTL,
SET_GET_PARAM(acq, 0x0, ACQ_CORE, CTL,
FSM_STOP_ACQ, SINGLE_BIT_PARAM, ACQ_FSM_STOP_MIN,
ACQ_FSM_STOP_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -735,7 +735,7 @@ RW_PARAM_FUNC(acq, fsm_stop) {
#define ACQ_DATA_DRIVEN_CHAN_MIN 0
#define ACQ_DATA_DRIVEN_CHAN_MAX (SMIO_ACQ_NUM_CHANNELS-1)
RW_PARAM_FUNC(acq, hw_data_trig_chan) {
SET_GET_PARAM(acq, WB_ACQ_CORE_CTRL_REGS_OFFS, ACQ_CORE, ACQ_CHAN_CTL,
SET_GET_PARAM(acq, 0x0, ACQ_CORE, ACQ_CHAN_CTL,
DTRIG_WHICH, MULT_BIT_PARAM, ACQ_DATA_DRIVEN_CHAN_MIN,
ACQ_DATA_DRIVEN_CHAN_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......
src/sm_io/modules/afc_diag/sm_io_afc_diag_exp.c
View file @ 1acccbcb
......@@ -42,13 +42,13 @@
/************************************************************/
RW_PARAM_FUNC(afc_diag, card_slot) {
SET_GET_PARAM(afc_diag, WB_AFC_DIAG_CTRL_RAW_REGS_OFFS, BPM_AFC_DIAG, GEO_ID,
SET_GET_PARAM(afc_diag, 0x0, BPM_AFC_DIAG, GEO_ID,
CARD_SLOT, MULT_BIT_PARAM, /* No minimum limit */,
/* No maximum limit */, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(afc_diag, ipmi_addr) {
SET_GET_PARAM(afc_diag, WB_AFC_DIAG_CTRL_RAW_REGS_OFFS, BPM_AFC_DIAG, GEO_ID,
SET_GET_PARAM(afc_diag, 0x0, BPM_AFC_DIAG, GEO_ID,
IPMI_ADDR, MULT_BIT_PARAM, /* No minimum limit */,
/* No maximum limit */, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......
src/sm_io/modules/dsp/sm_io_dsp_exp.c
View file @ 1acccbcb
......@@ -44,42 +44,42 @@
#define KX_PARAM_MIN 1
#define KX_PARAM_MAX ((1<<25)-1)
RW_PARAM_FUNC(dsp, kx) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, KX, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, 0x0, POS_CALC, KX, VAL, MULT_BIT_PARAM,
KX_PARAM_MIN, KX_PARAM_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define KY_PARAM_MIN 1
#define KY_PARAM_MAX ((1<<25)-1)
RW_PARAM_FUNC(dsp, ky) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, KY, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, 0x0, POS_CALC, KY, VAL, MULT_BIT_PARAM,
KY_PARAM_MIN, KY_PARAM_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define KSUM_PARAM_MIN 1
#define KSUM_PARAM_MAX ((1<<25)-1)
RW_PARAM_FUNC(dsp, ksum) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, KSUM, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, 0x0, POS_CALC, KSUM, VAL, MULT_BIT_PARAM,
KSUM_PARAM_MIN, KSUM_PARAM_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define DS_TBT_THRES_MIN 0
#define DS_TBT_THRES_MAX ((1<<26)-1)
RW_PARAM_FUNC(dsp, ds_tbt_thres) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DS_TBT_THRES, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DS_TBT_THRES, VAL, MULT_BIT_PARAM,
DS_TBT_THRES_MIN, DS_TBT_THRES_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define DS_FOFB_THRES_MIN 0
#define DS_FOFB_THRES_MAX ((1<<26)-1)
RW_PARAM_FUNC(dsp, ds_fofb_thres) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DS_FOFB_THRES, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DS_FOFB_THRES, VAL, MULT_BIT_PARAM,
DS_FOFB_THRES_MIN, DS_FOFB_THRES_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define DS_MONIT_THRES_MIN 0
#define DS_MONIT_THRES_MAX ((1<<26)-1)
RW_PARAM_FUNC(dsp, ds_monit_thres) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DS_MONIT_THRES, VAL, MULT_BIT_PARAM,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DS_MONIT_THRES, VAL, MULT_BIT_PARAM,
DS_MONIT_THRES_MIN, DS_MONIT_THRES_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -88,7 +88,7 @@ RW_PARAM_FUNC(dsp, ds_monit_thres) {
#define POS_CALC_DSP_MONIT_AMP_CH0_MASK ((1ULL<<32)-1)
RW_PARAM_FUNC(dsp, monit_amp_ch0) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DSP_MONIT_AMP_CH0, /* No field */,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DSP_MONIT_AMP_CH0, /* No field */,
MULT_BIT_PARAM, /* No minimum check*/, /* No maximum check */,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -98,7 +98,7 @@ RW_PARAM_FUNC(dsp, monit_amp_ch0) {
#define POS_CALC_DSP_MONIT_AMP_CH1_MASK ((1ULL<<32)-1)
RW_PARAM_FUNC(dsp, monit_amp_ch1) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DSP_MONIT_AMP_CH1, /* No field */,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DSP_MONIT_AMP_CH1, /* No field */,
MULT_BIT_PARAM, /* No minimum check*/, /* No maximum check */,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -108,7 +108,7 @@ RW_PARAM_FUNC(dsp, monit_amp_ch1) {
#define POS_CALC_DSP_MONIT_AMP_CH2_MASK ((1ULL<<32)-1)
RW_PARAM_FUNC(dsp, monit_amp_ch2) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DSP_MONIT_AMP_CH2, /* No field */,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DSP_MONIT_AMP_CH2, /* No field */,
MULT_BIT_PARAM, /* No minimum check*/, /* No maximum check */,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -118,7 +118,7 @@ RW_PARAM_FUNC(dsp, monit_amp_ch2) {
#define POS_CALC_DSP_MONIT_AMP_CH3_MASK ((1ULL<<32)-1)
RW_PARAM_FUNC(dsp, monit_amp_ch3) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DSP_MONIT_AMP_CH3, /* No field */,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DSP_MONIT_AMP_CH3, /* No field */,
MULT_BIT_PARAM, /* No minimum check*/, /* No maximum check */,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -128,7 +128,7 @@ RW_PARAM_FUNC(dsp, monit_amp_ch3) {
#define POS_CALC_DSP_MONIT_POS_X_MASK ((1ULL<<32)-1)
RW_PARAM_FUNC(dsp, monit_pos_x) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DSP_MONIT_POS_X, /* No field */,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DSP_MONIT_POS_X, /* No field */,
MULT_BIT_PARAM, /* No minimum check*/, /* No maximum check */,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -138,7 +138,7 @@ RW_PARAM_FUNC(dsp, monit_pos_x) {
#define POS_CALC_DSP_MONIT_POS_Y_MASK ((1ULL<<32)-1)
RW_PARAM_FUNC(dsp, monit_pos_y) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DSP_MONIT_POS_Y, /* No field */,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DSP_MONIT_POS_Y, /* No field */,
MULT_BIT_PARAM, /* No minimum check*/, /* No maximum check */,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -148,7 +148,7 @@ RW_PARAM_FUNC(dsp, monit_pos_y) {
#define POS_CALC_DSP_MONIT_POS_Q_MASK ((1ULL<<32)-1)
RW_PARAM_FUNC(dsp, monit_pos_q) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DSP_MONIT_POS_Q, /* No field */,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DSP_MONIT_POS_Q, /* No field */,
MULT_BIT_PARAM, /* No minimum check*/, /* No maximum check */,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -158,7 +158,7 @@ RW_PARAM_FUNC(dsp, monit_pos_q) {
#define POS_CALC_DSP_MONIT_POS_SUM_MASK ((1ULL<<32)-1)
RW_PARAM_FUNC(dsp, monit_pos_sum) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DSP_MONIT_POS_SUM, /* No field */,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DSP_MONIT_POS_SUM, /* No field */,
MULT_BIT_PARAM, /* No minimum check*/, /* No maximum check */,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -168,7 +168,7 @@ RW_PARAM_FUNC(dsp, monit_pos_sum) {
#define POS_CALC_DSP_MONIT_UPDT_MASK ((1ULL<<32)-1)
RW_PARAM_FUNC(dsp, monit_updt) {
SET_GET_PARAM(dsp, DSP_CTRL_REGS_OFFS, POS_CALC, DSP_MONIT_UPDT, /* No field */,
SET_GET_PARAM(dsp, 0x0, POS_CALC, DSP_MONIT_UPDT, /* No field */,
MULT_BIT_PARAM, /* No minimum check*/, /* No maximum check */,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......
src/sm_io/modules/fmc130m_4ch/sm_io_fmc130m_4ch_exp.c
View file @ 1acccbcb
......@@ -62,7 +62,7 @@
#define BPM_FMC130M_4CH_RAND_MAX 1 /* RAND enabled */
RW_PARAM_FUNC(fmc130m_4ch, adc_rand) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
ADC, RAND, SINGLE_BIT_PARAM,
BPM_FMC130M_4CH_RAND_MIN, BPM_FMC130M_4CH_RAND_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -72,7 +72,7 @@ RW_PARAM_FUNC(fmc130m_4ch, adc_rand) {
#define BPM_FMC130M_4CH_DITH_MAX 1 /* DITH enabled */
RW_PARAM_FUNC(fmc130m_4ch, adc_dith) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
ADC, DITH, SINGLE_BIT_PARAM,
BPM_FMC130M_4CH_DITH_MIN, BPM_FMC130M_4CH_DITH_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -82,7 +82,7 @@ RW_PARAM_FUNC(fmc130m_4ch, adc_dith) {
#define BPM_FMC130M_4CH_SHDN_MAX 1 /* SHDN enabled */
RW_PARAM_FUNC(fmc130m_4ch, adc_shdn) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
ADC, SHDN, SINGLE_BIT_PARAM,
BPM_FMC130M_4CH_SHDN_MIN, BPM_FMC130M_4CH_SHDN_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -92,7 +92,7 @@ RW_PARAM_FUNC(fmc130m_4ch, adc_shdn) {
#define BPM_FMC130M_4CH_PGA_MAX 1 /* PGA enabled */
RW_PARAM_FUNC(fmc130m_4ch, adc_pga) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
ADC, PGA, SINGLE_BIT_PARAM,
BPM_FMC130M_4CH_PGA_MIN, BPM_FMC130M_4CH_PGA_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -124,7 +124,7 @@ rw_param_format_fp rw_bpm_fmc130m_4ch_data_fmt_fp = _rw_bpm_fmc130m_4ch_data_fmt
#define WB_FMC_130M_4CH_CSR_DATA0_GLOBAL_W(val) WB_FMC_130M_4CH_CSR_DATA_GLOBAL_W(val)
#define WB_FMC_130M_4CH_CSR_DATA0_GLOBAL_R(val) WB_FMC_130M_4CH_CSR_DATA_GLOBAL_R(val)
RW_PARAM_FUNC(fmc130m_4ch, adc_data0) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
DATA0, GLOBAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
rw_bpm_fmc130m_4ch_data_fmt_fp, SET_FIELD);
......@@ -134,7 +134,7 @@ RW_PARAM_FUNC(fmc130m_4ch, adc_data0) {
#define WB_FMC_130M_4CH_CSR_DATA1_GLOBAL_W(val) WB_FMC_130M_4CH_CSR_DATA_GLOBAL_W(val)
#define WB_FMC_130M_4CH_CSR_DATA1_GLOBAL_R(val) WB_FMC_130M_4CH_CSR_DATA_GLOBAL_R(val)
RW_PARAM_FUNC(fmc130m_4ch, adc_data1) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
DATA1, GLOBAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
rw_bpm_fmc130m_4ch_data_fmt_fp, SET_FIELD);
......@@ -144,7 +144,7 @@ RW_PARAM_FUNC(fmc130m_4ch, adc_data1) {
#define WB_FMC_130M_4CH_CSR_DATA2_GLOBAL_W(val) WB_FMC_130M_4CH_CSR_DATA_GLOBAL_W(val)
#define WB_FMC_130M_4CH_CSR_DATA2_GLOBAL_R(val) WB_FMC_130M_4CH_CSR_DATA_GLOBAL_R(val)
RW_PARAM_FUNC(fmc130m_4ch, adc_data2) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
DATA2, GLOBAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
rw_bpm_fmc130m_4ch_data_fmt_fp, SET_FIELD);
......@@ -154,7 +154,7 @@ RW_PARAM_FUNC(fmc130m_4ch, adc_data2) {
#define WB_FMC_130M_4CH_CSR_DATA3_GLOBAL_W(val) WB_FMC_130M_4CH_CSR_DATA_GLOBAL_W(val)
#define WB_FMC_130M_4CH_CSR_DATA3_GLOBAL_R(val) WB_FMC_130M_4CH_CSR_DATA_GLOBAL_R(val)
RW_PARAM_FUNC(fmc130m_4ch, adc_data3) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
DATA3, GLOBAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
rw_bpm_fmc130m_4ch_data_fmt_fp, SET_FIELD);
......@@ -163,28 +163,28 @@ RW_PARAM_FUNC(fmc130m_4ch, adc_data3) {
/******************************** ADC Delay Values ****************************/
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_val0) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY0_CAL, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_val1) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY1_CAL, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_val2) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY2_CAL, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_val3) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY3_CAL, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -193,28 +193,28 @@ RW_PARAM_FUNC(fmc130m_4ch, adc_dly_val3) {
/******************************** ADC Delay Lines *****************************/
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_line0) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY0_CAL, LINE, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_line1) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY1_CAL, LINE, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_line2) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY2_CAL, LINE, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_line3) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY3_CAL, LINE, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -223,28 +223,28 @@ RW_PARAM_FUNC(fmc130m_4ch, adc_dly_line3) {
/******************************** ADC Delay Update ****************************/
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_updt0) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY0_CAL, UPDATE, SINGLE_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_updt1) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY1_CAL, UPDATE, SINGLE_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_updt2) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY2_CAL, UPDATE, SINGLE_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc130m_4ch, adc_dly_updt3) {
SET_GET_PARAM(fmc130m_4ch, FMC_130M_CTRL_REGS_OFFS, WB_FMC_130M_4CH_CSR,
SET_GET_PARAM(fmc130m_4ch, 0x0, WB_FMC_130M_4CH_CSR,
IDELAY3_CAL, UPDATE, SINGLE_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -333,7 +333,7 @@ err_adc_dly:
\
/* Delay value will be masked inside _fmc130m_4ch_set_adc_dly_ll */ \
\
return _fmc130m_4ch_set_adc_dly_ll (self, FMC_130M_CTRL_REGS_OFFS | \
return _fmc130m_4ch_set_adc_dly_ll (self, 0x0 | \
WB_FMC_130M_4CH_CSR_REG_IDELAY ## channel ## _CAL, dly_val, \
dly_type); \
\
......
src/sm_io/modules/fmc250m_4ch/sm_io_fmc250m_4ch_exp.c
View file @ 1acccbcb
......@@ -83,28 +83,28 @@ static int _rw_bpm_fmc250m_4ch_data_fmt (uint32_t *data)
rw_param_format_fp rw_bpm_fmc250m_4ch_data_fmt_fp = _rw_bpm_fmc250m_4ch_data_fmt;
RW_PARAM_FUNC(fmc250m_4ch, adc_data0) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
CH0_STA, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
rw_bpm_fmc250m_4ch_data_fmt_fp, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_data1) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
CH1_STA, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
rw_bpm_fmc250m_4ch_data_fmt_fp, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_data2) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
CH2_STA, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
rw_bpm_fmc250m_4ch_data_fmt_fp, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_data3) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
CH3_STA, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
rw_bpm_fmc250m_4ch_data_fmt_fp, SET_FIELD);
......@@ -114,28 +114,28 @@ RW_PARAM_FUNC(fmc250m_4ch, adc_data3) {
/******************************** ADC Delay Values ****************************/
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_val0) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY0_CAL, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_val1) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY1_CAL, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_val2) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY2_CAL, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_val3) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY3_CAL, VAL, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -144,28 +144,28 @@ RW_PARAM_FUNC(fmc250m_4ch, adc_dly_val3) {
/******************************** ADC Delay Lines *****************************/
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_line0) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY0_CAL, LINE, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_line1) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY1_CAL, LINE, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_line2) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY2_CAL, LINE, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_line3) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY3_CAL, LINE, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -174,28 +174,28 @@ RW_PARAM_FUNC(fmc250m_4ch, adc_dly_line3) {
/******************************** ADC Delay Update ****************************/
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_updt0) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY0_CAL, UPDATE, SINGLE_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_updt1) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY1_CAL, UPDATE, SINGLE_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_updt2) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY2_CAL, UPDATE, SINGLE_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(fmc250m_4ch, adc_dly_updt3) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
IDELAY3_CAL, UPDATE, SINGLE_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -284,7 +284,7 @@ err_adc_dly:
\
/* Delay value will be masked inside _fmc250m_4ch_set_adc_dly_ll */ \
\
return _fmc250m_4ch_set_adc_dly_ll (self, FMC_250M_CTRL_REGS_OFFS | \
return _fmc250m_4ch_set_adc_dly_ll (self, 0x0 | \
WB_FMC_250M_4CH_CSR_REG_IDELAY ## channel ## _CAL, dly_val, \
dly_type); \
\
......@@ -319,7 +319,7 @@ FMC250M_4CH_ADC_DLY_FUNC_HEADER(3)
#define BPM_FMC250M_4CH_RST_ADCS_MAX 1 /* Pulse RST_ADCS pin */
RW_PARAM_FUNC(fmc250m_4ch, rst_adcs) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
ADC_CTL, RST_ADCS, SINGLE_BIT_PARAM,
BPM_FMC250M_4CH_RST_ADCS_MIN, BPM_FMC250M_4CH_RST_ADCS_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -329,7 +329,7 @@ RW_PARAM_FUNC(fmc250m_4ch, rst_adcs) {
#define BPM_FMC250M_4CH_RST_DIV_ADCS_MAX 1 /* Pulse RST_DIV_ADCS pin */
RW_PARAM_FUNC(fmc250m_4ch, rst_div_adcs) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
ADC_CTL, RST_DIV_ADCS, SINGLE_BIT_PARAM,
BPM_FMC250M_4CH_RST_DIV_ADCS_MIN, BPM_FMC250M_4CH_RST_DIV_ADCS_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -339,7 +339,7 @@ RW_PARAM_FUNC(fmc250m_4ch, rst_div_adcs) {
#define BPM_FMC250M_4CH_SLEEP_ADCS_MAX 1 /* Pulse SLEEP_ADCS pin */
RW_PARAM_FUNC(fmc250m_4ch, sleep_adcs) {
SET_GET_PARAM(fmc250m_4ch, FMC_250M_CTRL_REGS_OFFS, WB_FMC_250M_4CH_CSR,
SET_GET_PARAM(fmc250m_4ch, 0x0, WB_FMC_250M_4CH_CSR,
ADC_CTL, SLEEP_ADCS, SINGLE_BIT_PARAM,
BPM_FMC250M_4CH_SLEEP_ADCS_MIN, BPM_FMC250M_4CH_SLEEP_ADCS_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......
src/sm_io/modules/fmc_active_clk/sm_io_fmc_active_clk_exp.c
View file @ 1acccbcb
......@@ -48,7 +48,7 @@ static smch_err_e smch_ad9510_cfg_defaults_compat (smch_ad9510_t *self,
#define BPM_FMC_ACTIVE_CLK_SI571_OE_MAX 1 /* SI571 Output enable */
RW_PARAM_FUNC(fmc_active_clk, si571_oe) {
SET_GET_PARAM(fmc_active_clk, FMC_ACTIVE_CLK_CTRL_REGS_OFFS, WB_FMC_ACTIVE_CLK_CSR,
SET_GET_PARAM(fmc_active_clk, 0x0, WB_FMC_ACTIVE_CLK_CSR,
CLK_DISTRIB, SI571_OE, SINGLE_BIT_PARAM,
BPM_FMC_ACTIVE_CLK_SI571_OE_MIN, BPM_FMC_ACTIVE_CLK_SI571_OE_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -58,7 +58,7 @@ RW_PARAM_FUNC(fmc_active_clk, si571_oe) {
#define BPM_FMC_ACTIVE_CLK_PLL_FUNC_MAX 1 /* PLL FUNCTION pin 1 */
RW_PARAM_FUNC(fmc_active_clk, pll_func) {
SET_GET_PARAM(fmc_active_clk, FMC_ACTIVE_CLK_CTRL_REGS_OFFS, WB_FMC_ACTIVE_CLK_CSR,
SET_GET_PARAM(fmc_active_clk, 0x0, WB_FMC_ACTIVE_CLK_CSR,
CLK_DISTRIB, PLL_FUNCTION, SINGLE_BIT_PARAM,
BPM_FMC_ACTIVE_CLK_PLL_FUNC_MIN, BPM_FMC_ACTIVE_CLK_PLL_FUNC_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -69,7 +69,7 @@ RW_PARAM_FUNC(fmc_active_clk, pll_func) {
#define BPM_FMC_ACTIVE_CLK_PLL_STATUS_MAX 1 /* PLL STATUS pin 1 */
RW_PARAM_FUNC(fmc_active_clk, pll_status) {
SET_GET_PARAM(fmc_active_clk, FMC_ACTIVE_CLK_CTRL_REGS_OFFS, WB_FMC_ACTIVE_CLK_CSR,
SET_GET_PARAM(fmc_active_clk, 0x0, WB_FMC_ACTIVE_CLK_CSR,
CLK_DISTRIB, PLL_STATUS, SINGLE_BIT_PARAM,
BPM_FMC_ACTIVE_CLK_PLL_STATUS_MIN, BPM_FMC_ACTIVE_CLK_PLL_STATUS_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -79,7 +79,7 @@ RW_PARAM_FUNC(fmc_active_clk, pll_status) {
#define BPM_FMC_ACTIVE_CLK_CLK_SEL_MAX 1 /* PLL CLK_SEL pin 1 */
RW_PARAM_FUNC(fmc_active_clk, clk_sel) {
SET_GET_PARAM(fmc_active_clk, FMC_ACTIVE_CLK_CTRL_REGS_OFFS, WB_FMC_ACTIVE_CLK_CSR,
SET_GET_PARAM(fmc_active_clk, 0x0, WB_FMC_ACTIVE_CLK_CSR,
CLK_DISTRIB, CLK_SEL, SINGLE_BIT_PARAM,
BPM_FMC_ACTIVE_CLK_CLK_SEL_MIN, BPM_FMC_ACTIVE_CLK_CLK_SEL_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......
src/sm_io/modules/fmc_adc_common/sm_io_fmc_adc_common_exp.c
View file @ 1acccbcb
......@@ -48,7 +48,7 @@
#define WB_FMC_ADC_COMMON_CSR_MONITOR_GLOBAL_R(reg) WBGEN2_GEN_READ(reg, 1, 3)
RW_PARAM_FUNC(fmc_adc_common, leds) {
SET_GET_PARAM(fmc_adc_common, FMC_130M_FMC_ADC_COMMON_OFFS, WB_FMC_ADC_COMMON_CSR,
SET_GET_PARAM(fmc_adc_common, 0x0, WB_FMC_ADC_COMMON_CSR,
MONITOR, GLOBAL, MULT_BIT_PARAM,
BPM_FMC_ADC_COMMON_LEDS_MIN, BPM_FMC_ADC_COMMON_LEDS_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -60,7 +60,7 @@ RW_PARAM_FUNC(fmc_adc_common, leds) {
#define BPM_FMC_ADC_COMMON_TEST_DATA_EN_MAX 1 /* TEST data enable on */
RW_PARAM_FUNC(fmc_adc_common, test_data_en) {
SET_GET_PARAM(fmc_adc_common, FMC_130M_FMC_ADC_COMMON_OFFS, WB_FMC_ADC_COMMON_CSR,
SET_GET_PARAM(fmc_adc_common, 0x0, WB_FMC_ADC_COMMON_CSR,
MONITOR, TEST_DATA_EN, SINGLE_BIT_PARAM,
BPM_FMC_ADC_COMMON_TEST_DATA_EN_MIN, BPM_FMC_ADC_COMMON_TEST_DATA_EN_MAX,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
......@@ -70,7 +70,7 @@ RW_PARAM_FUNC(fmc_adc_common, test_data_en) {
#define BPM_FMC_ADC_COMMON_TRIG_DIR_MAX 1 /* Trigger direction output */
RW_PARAM_FUNC(fmc_adc_common, trig_dir) {
SET_GET_PARAM(fmc_adc_common, FMC_130M_FMC_ADC_COMMON_OFFS, WB_FMC_ADC_COMMON_CSR,
SET_GET_PARAM(fmc_adc_common, 0x0, WB_FMC_ADC_COMMON_CSR,
TRIGGER, DIR, SINGLE_BIT_PARAM,
BPM_FMC_ADC_COMMON_TRIG_DIR_MIN, BPM_FMC_ADC_COMMON_TRIG_DIR_MAX,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
......@@ -80,7 +80,7 @@ RW_PARAM_FUNC(fmc_adc_common, trig_dir) {
#define BPM_FMC_ADC_COMMON_TRIG_TERM_MAX 1 /* Trigger termination enabled */
RW_PARAM_FUNC(fmc_adc_common, trig_term) {
SET_GET_PARAM(fmc_adc_common, FMC_130M_FMC_ADC_COMMON_OFFS, WB_FMC_ADC_COMMON_CSR,
SET_GET_PARAM(fmc_adc_common, 0x0, WB_FMC_ADC_COMMON_CSR,
TRIGGER, TERM, SINGLE_BIT_PARAM,
BPM_FMC_ADC_COMMON_TRIG_TERM_MIN, BPM_FMC_ADC_COMMON_TRIG_TERM_MAX,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
......@@ -90,7 +90,7 @@ RW_PARAM_FUNC(fmc_adc_common, trig_term) {
#define BPM_FMC_ADC_COMMON_TRIG_VAL_MAX 1 /* Trigger value 1 */
RW_PARAM_FUNC(fmc_adc_common, trig_val) {
SET_GET_PARAM(fmc_adc_common, FMC_130M_FMC_ADC_COMMON_OFFS, WB_FMC_ADC_COMMON_CSR,
SET_GET_PARAM(fmc_adc_common, 0x0, WB_FMC_ADC_COMMON_CSR,
TRIGGER, TRIG_VAL, SINGLE_BIT_PARAM,
BPM_FMC_ADC_COMMON_TRIG_VAL_MIN, BPM_FMC_ADC_COMMON_TRIG_VAL_MAX,
NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
......
src/sm_io/modules/swap/sm_io_swap_exp.c
View file @ 1acccbcb
......@@ -53,21 +53,21 @@
#define BPM_SWAP_CTRL_MODE_GLOBAL_W(val) (BPM_SWAP_CTRL_MODE1_W(val) | BPM_SWAP_CTRL_MODE2_W(val))
#define BPM_SWAP_CTRL_MODE_GLOBAL_R(val) (BPM_SWAP_CTRL_MODE1_R(val) | BPM_SWAP_CTRL_MODE2_R(val))
RW_PARAM_FUNC(swap, sw) {
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, CTRL, MODE_GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, 0x0, BPM_SWAP, CTRL, MODE_GLOBAL, MULT_BIT_PARAM,
SW_MIN, SW_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define BPM_SW_EN_MIN 0 /* Switching enabled */
#define BPM_SW_EN_MAX 1 /* Switching disabled */
RW_PARAM_FUNC(swap, sw_en) {
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, CTRL, CLK_SWAP_EN, SINGLE_BIT_PARAM,
SET_GET_PARAM(swap, 0x0, BPM_SWAP, CTRL, CLK_SWAP_EN, SINGLE_BIT_PARAM,
BPM_SW_EN_MIN, BPM_SW_EN_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define BPM_SWAP_DIV_F_MIN 1
#define BPM_SWAP_DIV_F_MAX ((1<<16)-1)
RW_PARAM_FUNC(swap, div_clk) {
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, CTRL, SWAP_DIV_F, MULT_BIT_PARAM,
SET_GET_PARAM(swap, 0x0, BPM_SWAP, CTRL, SWAP_DIV_F, MULT_BIT_PARAM,
BPM_SWAP_DIV_F_MIN, BPM_SWAP_DIV_F_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -79,7 +79,7 @@ RW_PARAM_FUNC(swap, div_clk) {
#define BPM_SWAP_DLY_GLOBAL_W(val) (BPM_SWAP_DLY_1_W(val) | BPM_SWAP_DLY_2_W(val))
#define BPM_SWAP_DLY_GLOBAL_R(val) (BPM_SWAP_DLY_1_R(val) | BPM_SWAP_DLY_2_R(val))
RW_PARAM_FUNC(swap, sw_dly) {
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, DLY, GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, 0x0, BPM_SWAP, DLY, GLOBAL, MULT_BIT_PARAM,
BPM_SWAP_SW_DLY_MIN, BPM_SWAP_SW_DLY_MAX, NO_CHK_FUNC, NO_FMT_FUNC,
SET_FIELD);
}
......@@ -89,14 +89,14 @@ RW_PARAM_FUNC(swap, sw_dly) {
#define BPM_SWAP_WDW_CTL_EN_GLOBAL (BPM_SWAP_WDW_CTL_USE | BPM_SWAP_WDW_CTL_SWCLK_EXT)
RW_PARAM_FUNC(swap, wdw_en) {
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, WDW_CTL, EN_GLOBAL, SINGLE_BIT_PARAM,
SET_GET_PARAM(swap, 0x0, BPM_SWAP, WDW_CTL, EN_GLOBAL, SINGLE_BIT_PARAM,
BPM_SWAP_WDW_EN_MIN, BPM_SWAP_WDW_EN_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
#define BPM_SWAP_WDW_DLY_MIN 0
#define BPM_SWAP_WDW_DLY_MAX ((1<<16)-1)
RW_PARAM_FUNC(swap, wdw_dly) {
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, WDW_CTL, DLY, MULT_BIT_PARAM,
SET_GET_PARAM(swap, 0x0, BPM_SWAP, WDW_CTL, DLY, MULT_BIT_PARAM,
BPM_SWAP_WDW_DLY_MIN, BPM_SWAP_WDW_DLY_MAX, NO_CHK_FUNC, NO_FMT_FUNC, SET_FIELD);
}
......@@ -132,7 +132,7 @@ rw_param_check_fp rw_bpm_swap_gain_chk_fp = _rw_bpm_swap_gain_chk;
#define BPM_SWAP_A_GLOBAL_W(val) (val)
#define BPM_SWAP_A_GLOBAL_R(val) (val)
RW_PARAM_FUNC(swap, gain_a) {
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, A, GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, 0x0, BPM_SWAP, A, GLOBAL, MULT_BIT_PARAM,
BPM_SWAP_GAIN_MIN, BPM_SWAP_GAIN_MAX, rw_bpm_swap_gain_chk_fp,
NO_FMT_FUNC, SET_FIELD);
}
......@@ -141,7 +141,7 @@ RW_PARAM_FUNC(swap, gain_a) {
#define BPM_SWAP_B_GLOBAL_W(val) (val)
#define BPM_SWAP_B_GLOBAL_R(val) (val)
RW_PARAM_FUNC(swap, gain_b) {
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, B, GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, 0x0, BPM_SWAP, B, GLOBAL, MULT_BIT_PARAM,
BPM_SWAP_GAIN_MIN, BPM_SWAP_GAIN_MAX, rw_bpm_swap_gain_chk_fp,
NO_FMT_FUNC, SET_FIELD);
}
......@@ -150,7 +150,7 @@ RW_PARAM_FUNC(swap, gain_b) {
#define BPM_SWAP_C_GLOBAL_W(val) (val)
#define BPM_SWAP_C_GLOBAL_R(val) (val)
RW_PARAM_FUNC(swap, gain_c) {
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, C, GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, 0x0, BPM_SWAP, C, GLOBAL, MULT_BIT_PARAM,
BPM_SWAP_GAIN_MIN, BPM_SWAP_GAIN_MAX, rw_bpm_swap_gain_chk_fp,
NO_FMT_FUNC, SET_FIELD);
}
......@@ -159,7 +159,7 @@ RW_PARAM_FUNC(swap, gain_c) {
#define BPM_SWAP_D_GLOBAL_W(val) (val)
#define BPM_SWAP_D_GLOBAL_R(val) (val)
RW_PARAM_FUNC(swap, gain_d) {
SET_GET_PARAM(swap, DSP_BPM_SWAP_OFFS, BPM_SWAP, D, GLOBAL, MULT_BIT_PARAM,
SET_GET_PARAM(swap, 0x0, BPM_SWAP, D, GLOBAL, MULT_BIT_PARAM,
BPM_SWAP_GAIN_MIN, BPM_SWAP_GAIN_MAX, rw_bpm_swap_gain_chk_fp,
NO_FMT_FUNC, SET_FIELD);
}
......
src/sm_io/modules/trigger_iface/sm_io_trigger_iface_exp.c
View file @ 1acccbcb
......@@ -48,7 +48,7 @@
#define BPM_TRIGGER_IFACE_DIR_MIN 0 /* Bidirection Buffer set to Output */
#define BPM_TRIGGER_IFACE_DIR_MAX 1 /* Bidirection Buffer set to Input */
RW_PARAM_FUNC(trigger_iface, dir) {
SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
SET_GET_PARAM_CHANNEL(trigger_iface, 0x0, WB_TRIG_IFACE,
CH0_CTL, DIR, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, SINGLE_BIT_PARAM,
BPM_TRIGGER_IFACE_DIR_MIN, BPM_TRIGGER_IFACE_DIR_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -57,7 +57,7 @@ RW_PARAM_FUNC(trigger_iface, dir) {
#define BPM_TRIGGER_IFACE_DIR_POL_MIN 0 /* Direction polarity kept */
#define BPM_TRIGGER_IFACE_DIR_POL_MAX 1 /* Direction polarity reversed */
RW_PARAM_FUNC(trigger_iface, dir_pol) {
SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
SET_GET_PARAM_CHANNEL(trigger_iface, 0x0, WB_TRIG_IFACE,
CH0_CTL, DIR_POL, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, SINGLE_BIT_PARAM,
BPM_TRIGGER_IFACE_DIR_POL_MIN, BPM_TRIGGER_IFACE_DIR_POL_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -66,7 +66,7 @@ RW_PARAM_FUNC(trigger_iface, dir_pol) {
#define BPM_TRIGGER_IFACE_RCV_COUNT_RST_MIN 0 /* Receive Counter Reset */
#define BPM_TRIGGER_IFACE_RCV_COUNT_RST_MAX 1 /* Receive Counter Reset */
RW_PARAM_FUNC(trigger_iface, rcv_count_rst) {
SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
SET_GET_PARAM_CHANNEL(trigger_iface, 0x0, WB_TRIG_IFACE,
CH0_CTL, RCV_COUNT_RST, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, SINGLE_BIT_PARAM,
BPM_TRIGGER_IFACE_RCV_COUNT_RST_MIN, BPM_TRIGGER_IFACE_RCV_COUNT_RST_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -75,7 +75,7 @@ RW_PARAM_FUNC(trigger_iface, rcv_count_rst) {
#define BPM_TRIGGER_IFACE_TRANSM_COUNT_RST_MIN 0 /* Transmit Counter Reset */
#define BPM_TRIGGER_IFACE_TRANSM_COUNT_RST_MAX 1 /* Transmit Counter Reset */
RW_PARAM_FUNC(trigger_iface, transm_count_rst) {
SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
SET_GET_PARAM_CHANNEL(trigger_iface, 0x0, WB_TRIG_IFACE,
CH0_CTL, TRANSM_COUNT_RST, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, SINGLE_BIT_PARAM,
BPM_TRIGGER_IFACE_TRANSM_COUNT_RST_MIN, BPM_TRIGGER_IFACE_TRANSM_COUNT_RST_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -84,7 +84,7 @@ RW_PARAM_FUNC(trigger_iface, transm_count_rst) {
#define BPM_TRIGGER_IFACE_RCV_LEN_MIN 0 /* Receiver Debounce Length */
#define BPM_TRIGGER_IFACE_RCV_LEN_MAX ((1 << 8) -1) /* Receiver Debounce Length */
RW_PARAM_FUNC(trigger_iface, rcv_len) {
SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
SET_GET_PARAM_CHANNEL(trigger_iface, 0x0, WB_TRIG_IFACE,
CH0_CFG, RCV_LEN, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, MULT_BIT_PARAM,
BPM_TRIGGER_IFACE_RCV_LEN_MIN, BPM_TRIGGER_IFACE_RCV_LEN_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -93,21 +93,21 @@ RW_PARAM_FUNC(trigger_iface, rcv_len) {
#define BPM_TRIGGER_IFACE_TRANSM_LEN_MIN 0 /* Receiver Debounce Length */
#define BPM_TRIGGER_IFACE_TRANSM_LEN_MAX ((1 << 8) -1) /* Receiver Debounce Length */
RW_PARAM_FUNC(trigger_iface, transm_len) {
SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
SET_GET_PARAM_CHANNEL(trigger_iface, 0x0, WB_TRIG_IFACE,
CH0_CFG, TRANSM_LEN, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(trigger_iface, count_rcv) {
SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
SET_GET_PARAM_CHANNEL(trigger_iface, 0x0, WB_TRIG_IFACE,
CH0_COUNT, RCV, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
}
RW_PARAM_FUNC(trigger_iface, count_transm) {
SET_GET_PARAM_CHANNEL(trigger_iface, WB_TRIGGER_IFACE_RAW_REG_OFFS, WB_TRIG_IFACE,
SET_GET_PARAM_CHANNEL(trigger_iface, 0x0, WB_TRIG_IFACE,
CH0_COUNT, TRANSM, TRIGGER_IFACE_CHAN_OFFSET, TRIGGER_IFACE_NUM_CHAN, MULT_BIT_PARAM,
/* no minimum value */, /* no maximum value */, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......
src/sm_io/modules/trigger_mux/sm_io_trigger_mux_exp.c
View file @ 1acccbcb
......@@ -48,7 +48,7 @@
#define BPM_TRIGGER_MUX_RCV_SRC_MIN 0 /* Trigger Source Selection (= Trigger Backplane) */
#define BPM_TRIGGER_MUX_RCV_SRC_MAX 1 /* Trigger Source Selection (= FPGA internal) */
RW_PARAM_FUNC(trigger_mux, rcv_src) {
SET_GET_PARAM_CHANNEL(trigger_mux, WB_TRIGGER_MUX_RAW_REG_OFFS, WB_TRIG_MUX,
SET_GET_PARAM_CHANNEL(trigger_mux, 0x0, WB_TRIG_MUX,
CH0_CTL, RCV_SRC, TRIGGER_MUX_CHAN_OFFSET, TRIGGER_MUX_NUM_CHAN, SINGLE_BIT_PARAM,
BPM_TRIGGER_MUX_RCV_SRC_MIN, BPM_TRIGGER_MUX_RCV_SRC_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -57,7 +57,7 @@ RW_PARAM_FUNC(trigger_mux, rcv_src) {
#define BPM_TRIGGER_MUX_RCV_IN_SEL_MIN 0 /* Minimum selection */
#define BPM_TRIGGER_MUX_RCV_IN_SEL_MAX ((1 << 8) -1) /* Maximum selection */
RW_PARAM_FUNC(trigger_mux, rcv_in_sel) {
SET_GET_PARAM_CHANNEL(trigger_mux, WB_TRIGGER_MUX_RAW_REG_OFFS, WB_TRIG_MUX,
SET_GET_PARAM_CHANNEL(trigger_mux, 0x0, WB_TRIG_MUX,
CH0_CTL, RCV_IN_SEL, TRIGGER_MUX_CHAN_OFFSET, TRIGGER_MUX_NUM_CHAN, MULT_BIT_PARAM,
BPM_TRIGGER_MUX_RCV_IN_SEL_MIN, BPM_TRIGGER_MUX_RCV_IN_SEL_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -66,7 +66,7 @@ RW_PARAM_FUNC(trigger_mux, rcv_in_sel) {
#define BPM_TRIGGER_MUX_TRANSM_SRC_MIN 0 /* Trigger Source Selection (= Trigger Backplane) */
#define BPM_TRIGGER_MUX_TRANSM_SRC_MAX 1 /* Trigger Source Selection (= FPGA internal) */
RW_PARAM_FUNC(trigger_mux, transm_src) {
SET_GET_PARAM_CHANNEL(trigger_mux, WB_TRIGGER_MUX_RAW_REG_OFFS, WB_TRIG_MUX,
SET_GET_PARAM_CHANNEL(trigger_mux, 0x0, WB_TRIG_MUX,
CH0_CTL, TRANSM_SRC, TRIGGER_MUX_CHAN_OFFSET, TRIGGER_MUX_NUM_CHAN, SINGLE_BIT_PARAM,
BPM_TRIGGER_MUX_TRANSM_SRC_MIN, BPM_TRIGGER_MUX_TRANSM_SRC_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......@@ -75,7 +75,7 @@ RW_PARAM_FUNC(trigger_mux, transm_src) {
#define BPM_TRIGGER_MUX_TRANSM_OUT_SEL_MIN 0 /* Minimum selection */
#define BPM_TRIGGER_MUX_TRANSM_OUT_SEL_MAX ((1 << 8) -1) /* Maximum selection */
RW_PARAM_FUNC(trigger_mux, transm_out_sel) {
SET_GET_PARAM_CHANNEL(trigger_mux, WB_TRIGGER_MUX_RAW_REG_OFFS, WB_TRIG_MUX,
SET_GET_PARAM_CHANNEL(trigger_mux, 0x0, WB_TRIG_MUX,
CH0_CTL, TRANSM_OUT_SEL, TRIGGER_MUX_CHAN_OFFSET, TRIGGER_MUX_NUM_CHAN, MULT_BIT_PARAM,
BPM_TRIGGER_MUX_TRANSM_OUT_SEL_MIN, BPM_TRIGGER_MUX_TRANSM_OUT_SEL_MAX, NO_CHK_FUNC,
NO_FMT_FUNC, SET_FIELD);
......
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