Wishbone slave for FMC ADC 250MS/s core
H/W Address | Type | Name | VHDL/Verilog prefix | C prefix |
---|---|---|---|---|
0x0 | REG | Global ADC Status register | wb_fmc_250m_4ch_csr_adc_sta | ADC_STA |
0x1 | REG | Global ADC Control register | wb_fmc_250m_4ch_csr_adc_ctl | ADC_CTL |
0x2 | REG | Channel 0 status register | wb_fmc_250m_4ch_csr_ch0_sta | CH0_STA |
0x3 | REG | Channel 0 fine delay register | wb_fmc_250m_4ch_csr_ch0_fn_dly | CH0_FN_DLY |
0x4 | REG | Channel 0 fine delay selection | wb_fmc_250m_4ch_csr_ch0_fn_sel | CH0_FN_SEL |
0x5 | REG | Channel 0 coarse delay register | wb_fmc_250m_4ch_csr_ch0_cs_dly | CH0_CS_DLY |
0x6 | REG | Channel 1 status register | wb_fmc_250m_4ch_csr_ch1_sta | CH1_STA |
0x7 | REG | Channel 1 fine delay register | wb_fmc_250m_4ch_csr_ch1_fn_dly | CH1_FN_DLY |
0x8 | REG | Channel 1 fine delay selection | wb_fmc_250m_4ch_csr_ch1_fn_sel | CH1_FN_SEL |
0x9 | REG | Channel 1 coarse delay register | wb_fmc_250m_4ch_csr_ch1_cs_dly | CH1_CS_DLY |
0xa | REG | Channel 2 status register | wb_fmc_250m_4ch_csr_ch2_sta | CH2_STA |
0xb | REG | Channel 2 fine delay register | wb_fmc_250m_4ch_csr_ch2_fn_dly | CH2_FN_DLY |
0xc | REG | Channel 2 fine delay selection | wb_fmc_250m_4ch_csr_ch2_fn_sel | CH2_FN_SEL |
0xd | REG | Channel 2 coarse delay register | wb_fmc_250m_4ch_csr_ch2_cs_dly | CH2_CS_DLY |
0xe | REG | Channel 3 status register | wb_fmc_250m_4ch_csr_ch3_sta | CH3_STA |
0xf | REG | Channel 3 fine delay register | wb_fmc_250m_4ch_csr_ch3_fn_dly | CH3_FN_DLY |
0x10 | REG | Channel 3 fine delay selection | wb_fmc_250m_4ch_csr_ch3_fn_sel | CH3_FN_SEL |
0x11 | REG | Channel 3 coarse delay register | wb_fmc_250m_4ch_csr_ch3_cs_dly | CH3_CS_DLY |
0x12 | REG | FMC temperature monitor register | wb_fmc_250m_4ch_csr_temp | TEMP |
→ | rst_n_i | Global ADC Status register: | ||
→ | clk_sys_i | wb_fmc_250m_4ch_csr_adc_sta_clk_chains_i[3:0] | ⇐ | |
⇒ | wb_adr_i[4:0] | wb_fmc_250m_4ch_csr_adc_sta_reserved_clk_chains_i[3:0] | ⇐ | |
⇒ | wb_dat_i[31:0] | wb_fmc_250m_4ch_csr_adc_sta_data_chains_i[3:0] | ⇐ | |
⇐ | wb_dat_o[31:0] | wb_fmc_250m_4ch_csr_adc_sta_reserved_data_chains_i[3:0] | ⇐ | |
→ | wb_cyc_i | wb_fmc_250m_4ch_csr_adc_sta_adc_pkt_size_i[15:0] | ⇐ | |
⇒ | wb_sel_i[3:0] | |||
→ | wb_stb_i | Global ADC Control register: | ||
→ | wb_we_i | wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_o | → | |
← | wb_ack_o | wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_o | → | |
← | wb_stall_o | wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_o | → | |
wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_o | → | |||
wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_o | → | |||
wb_fmc_250m_4ch_csr_adc_ctl_reserved_i[26:0] | ⇐ | |||
Channel 0 status register: | ||||
wb_fmc_250m_4ch_csr_ch0_sta_val_i[15:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch0_sta_reserved_i[15:0] | ⇐ | |||
Channel 0 fine delay register: | ||||
wb_fmc_250m_4ch_csr_ch0_fn_dly_clk_chain_dly_o[4:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_clk_chain_dly_i[4:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_clk_chain_dly_load_o | → | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_clk_chain_dly_i[2:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_data_chain_dly_o[4:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_data_chain_dly_i[4:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_data_chain_dly_load_o | → | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_data_chain_dly_i[2:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_clk_incdec_dly_o[5:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_data_incdec_dly_o[5:0] | ⇒ | |||
Channel 0 fine delay selection: | ||||
wb_fmc_250m_4ch_csr_ch0_fn_sel_line_o[16:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch0_fn_sel_reserved_i[14:0] | ⇐ | |||
Channel 0 coarse delay register: | ||||
wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_o[1:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_fe_dly_o[5:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_o[1:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_rg_dly_o[21:0] | ⇒ | |||
Channel 1 status register: | ||||
wb_fmc_250m_4ch_csr_ch1_sta_val_i[15:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch1_sta_reserved_i[15:0] | ⇐ | |||
Channel 1 fine delay register: | ||||
wb_fmc_250m_4ch_csr_ch1_fn_dly_clk_chain_dly_o[4:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_clk_chain_dly_i[4:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_clk_chain_dly_load_o | → | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_clk_chain_dly_i[2:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_data_chain_dly_o[4:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_data_chain_dly_i[4:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_data_chain_dly_load_o | → | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_data_chain_dly_i[2:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_clk_incdec_dly_o[5:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_data_incdec_dly_o[5:0] | ⇒ | |||
Channel 1 fine delay selection: | ||||
wb_fmc_250m_4ch_csr_ch1_fn_sel_line_o[16:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch1_fn_sel_reserved_i[14:0] | ⇐ | |||
Channel 1 coarse delay register: | ||||
wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_o[1:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_fe_dly_o[5:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_o[1:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_rg_dly_o[21:0] | ⇒ | |||
Channel 2 status register: | ||||
wb_fmc_250m_4ch_csr_ch2_sta_val_i[15:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch2_sta_reserved_i[15:0] | ⇐ | |||
Channel 2 fine delay register: | ||||
wb_fmc_250m_4ch_csr_ch2_fn_dly_clk_chain_dly_o[4:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_clk_chain_dly_i[4:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_clk_chain_dly_load_o | → | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_clk_chain_dly_i[2:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_data_chain_dly_o[4:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_data_chain_dly_i[4:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_data_chain_dly_load_o | → | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_data_chain_dly_i[2:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_clk_incdec_dly_o[5:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_data_incdec_dly_o[5:0] | ⇒ | |||
Channel 2 fine delay selection: | ||||
wb_fmc_250m_4ch_csr_ch2_fn_sel_line_o[16:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch2_fn_sel_reserved_i[14:0] | ⇐ | |||
Channel 2 coarse delay register: | ||||
wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_o[1:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_fe_dly_o[5:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_o[1:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_rg_dly_o[21:0] | ⇒ | |||
Channel 3 status register: | ||||
wb_fmc_250m_4ch_csr_ch3_sta_val_i[15:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch3_sta_reserved_i[15:0] | ⇐ | |||
Channel 3 fine delay register: | ||||
wb_fmc_250m_4ch_csr_ch3_fn_dly_clk_chain_dly_o[4:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_clk_chain_dly_i[4:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_clk_chain_dly_load_o | → | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_clk_chain_dly_i[2:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_data_chain_dly_o[4:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_data_chain_dly_i[4:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_data_chain_dly_load_o | → | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_data_chain_dly_i[2:0] | ⇐ | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_clk_incdec_dly_o[5:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_o | → | |||
wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_data_incdec_dly_o[5:0] | ⇒ | |||
Channel 3 fine delay selection: | ||||
wb_fmc_250m_4ch_csr_ch3_fn_sel_line_o[16:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch3_fn_sel_reserved_i[14:0] | ⇐ | |||
Channel 3 coarse delay register: | ||||
wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_o[1:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_fe_dly_o[5:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_o[1:0] | ⇒ | |||
wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_rg_dly_o[21:0] | ⇒ | |||
FMC temperature monitor register: | ||||
wb_fmc_250m_4ch_csr_temp_mon_dev_i | ← |
HW prefix: | wb_fmc_250m_4ch_csr_adc_sta |
HW address: | 0x0 |
C prefix: | ADC_STA |
C offset: | 0x0 |
Global ADC status register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
ADC_PKT_SIZE[15:8] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
ADC_PKT_SIZE[7:0] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | ||||||
RESERVED_DATA_CHAINS[3:0] | DATA_CHAINS[3:0] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED_CLK_CHAINS[3:0] | CLK_CHAINS[3:0] |
HW prefix: | wb_fmc_250m_4ch_csr_adc_ctl |
HW address: | 0x1 |
C prefix: | ADC_CTL |
C offset: | 0x4 |
Global ADC control register.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED[26:19] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED[18:11] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
RESERVED[10:3] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
RESERVED[2:0] | SLEEP_ADCS | RST_DIV_ADCS | RST_ADCS | UPDATE_DATA_DLY | UPDATE_CLK_DLY |
HW prefix: | wb_fmc_250m_4ch_csr_ch0_sta |
HW address: | 0x2 |
C prefix: | CH0_STA |
C offset: | 0x8 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED[15:8] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED[7:0] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
VAL[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
VAL[7:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch0_fn_dly |
HW address: | 0x3 |
C prefix: | CH0_FN_DLY |
C offset: | 0xc |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||
RESERVED_DATA_INCDEC_DLY[5:0] | DEC_DATA_CHAIN_DLY | INC_DATA_CHAIN_DLY |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||
RESERVED_CLK_INCDEC_DLY[5:0] | DEC_CLK_CHAIN_DLY | INC_CLK_CHAIN_DLY |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | ||||||
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch0_fn_sel |
HW address: | 0x4 |
C prefix: | CH0_FN_SEL |
C offset: | 0x10 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED[14:7] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | ||||||
RESERVED[6:0] | LINE[16:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
LINE[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
LINE[7:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch0_cs_dly |
HW address: | 0x5 |
C prefix: | CH0_CS_DLY |
C offset: | 0x14 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED_RG_DLY[21:14] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED_RG_DLY[13:6] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | ||||||
RESERVED_RG_DLY[5:0] | RG_DLY[1:0] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED_FE_DLY[5:0] | FE_DLY[1:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch1_sta |
HW address: | 0x6 |
C prefix: | CH1_STA |
C offset: | 0x18 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED[15:8] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED[7:0] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
VAL[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
VAL[7:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch1_fn_dly |
HW address: | 0x7 |
C prefix: | CH1_FN_DLY |
C offset: | 0x1c |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||
RESERVED_DATA_INCDEC_DLY[5:0] | DEC_DATA_CHAIN_DLY | INC_DATA_CHAIN_DLY |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||
RESERVED_CLK_INCDEC_DLY[5:0] | DEC_CLK_CHAIN_DLY | INC_CLK_CHAIN_DLY |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | ||||||
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch1_fn_sel |
HW address: | 0x8 |
C prefix: | CH1_FN_SEL |
C offset: | 0x20 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED[14:7] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | ||||||
RESERVED[6:0] | LINE[16:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
LINE[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
LINE[7:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch1_cs_dly |
HW address: | 0x9 |
C prefix: | CH1_CS_DLY |
C offset: | 0x24 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED_RG_DLY[21:14] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED_RG_DLY[13:6] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | ||||||
RESERVED_RG_DLY[5:0] | RG_DLY[1:0] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED_FE_DLY[5:0] | FE_DLY[1:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch2_sta |
HW address: | 0xa |
C prefix: | CH2_STA |
C offset: | 0x28 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED[15:8] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED[7:0] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
VAL[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
VAL[7:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch2_fn_dly |
HW address: | 0xb |
C prefix: | CH2_FN_DLY |
C offset: | 0x2c |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||
RESERVED_DATA_INCDEC_DLY[5:0] | DEC_DATA_CHAIN_DLY | INC_DATA_CHAIN_DLY |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||
RESERVED_CLK_INCDEC_DLY[5:0] | DEC_CLK_CHAIN_DLY | INC_CLK_CHAIN_DLY |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | ||||||
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch2_fn_sel |
HW address: | 0xc |
C prefix: | CH2_FN_SEL |
C offset: | 0x30 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED[14:7] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | ||||||
RESERVED[6:0] | LINE[16:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
LINE[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
LINE[7:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch2_cs_dly |
HW address: | 0xd |
C prefix: | CH2_CS_DLY |
C offset: | 0x34 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED_RG_DLY[21:14] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED_RG_DLY[13:6] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | ||||||
RESERVED_RG_DLY[5:0] | RG_DLY[1:0] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED_FE_DLY[5:0] | FE_DLY[1:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch3_sta |
HW address: | 0xe |
C prefix: | CH3_STA |
C offset: | 0x38 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED[15:8] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED[7:0] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
VAL[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
VAL[7:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch3_fn_dly |
HW address: | 0xf |
C prefix: | CH3_FN_DLY |
C offset: | 0x3c |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||
RESERVED_DATA_INCDEC_DLY[5:0] | DEC_DATA_CHAIN_DLY | INC_DATA_CHAIN_DLY |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||
RESERVED_CLK_INCDEC_DLY[5:0] | DEC_CLK_CHAIN_DLY | INC_CLK_CHAIN_DLY |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | ||||||
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch3_fn_sel |
HW address: | 0x10 |
C prefix: | CH3_FN_SEL |
C offset: | 0x40 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED[14:7] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | ||||||
RESERVED[6:0] | LINE[16:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
LINE[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
LINE[7:0] |
HW prefix: | wb_fmc_250m_4ch_csr_ch3_cs_dly |
HW address: | 0x11 |
C prefix: | CH3_CS_DLY |
C offset: | 0x44 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
RESERVED_RG_DLY[21:14] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
RESERVED_RG_DLY[13:6] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | ||||||
RESERVED_RG_DLY[5:0] | RG_DLY[1:0] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
RESERVED_FE_DLY[5:0] | FE_DLY[1:0] |
HW prefix: | wb_fmc_250m_4ch_csr_temp |
HW address: | 0x12 |
C prefix: | TEMP |
C offset: | 0x48 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | MON_DEV |