wb_fmc_active_clk_csr

FMC Active Clock registers

Wishbone slave for FMC Active Clock

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Clock distribution control register
3.2. Dummy

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Clock distribution control register wb_fmc_active_clk_csr_clk_distrib CLK_DISTRIB
0x1 REG Dummy wb_fmc_active_clk_csr_dummy DUMMY

2. HDL symbol

rst_n_i Clock distribution control register:
clk_sys_i wb_fmc_active_clk_csr_clk_distrib_si571_oe_o
wb_adr_i wb_fmc_active_clk_csr_clk_distrib_pll_function_o
wb_dat_i[31:0] wb_fmc_active_clk_csr_clk_distrib_pll_status_i
wb_dat_o[31:0] wb_fmc_active_clk_csr_clk_distrib_clk_sel_o
wb_cyc_i wb_fmc_active_clk_csr_clk_distrib_reserved_i[27:0]
wb_sel_i[3:0]  
wb_stb_i Dummy:
wb_we_i wb_fmc_active_clk_csr_dummy_reserved_i[31:0]
wb_ack_o
wb_stall_o

3. Register description

3.1. Clock distribution control register

HW prefix: wb_fmc_active_clk_csr_clk_distrib
HW address: 0x0
C prefix: CLK_DISTRIB
C offset: 0x0
31 30 29 28 27 26 25 24
RESERVED[27:20]
23 22 21 20 19 18 17 16
RESERVED[19:12]
15 14 13 12 11 10 9 8
RESERVED[11:4]
7 6 5 4 3 2 1 0
RESERVED[3:0] CLK_SEL PLL_STATUS PLL_FUNCTION SI571_OE

3.2. Dummy

HW prefix: wb_fmc_active_clk_csr_dummy
HW address: 0x1
C prefix: DUMMY
C offset: 0x4
31 30 29 28 27 26 25 24
RESERVED[31:24]
23 22 21 20 19 18 17 16
RESERVED[23:16]
15 14 13 12 11 10 9 8
RESERVED[15:8]
7 6 5 4 3 2 1 0
RESERVED[7:0]