wb_fmc_adc_common_csr

FMC ADC Common registers

Wishbone slave for FMC ADC Common

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Status register
3.2. Trigger control
3.3. Monitor and FMC status control register

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Status register wb_fmc_adc_common_csr_fmc_status FMC_STATUS
0x1 REG Trigger control wb_fmc_adc_common_csr_trigger TRIGGER
0x2 REG Monitor and FMC status control register wb_fmc_adc_common_csr_monitor MONITOR

2. HDL symbol

rst_n_i Status register:
clk_sys_i wb_fmc_adc_common_csr_fmc_status_mmcm_locked_i
wb_adr_i[1:0] wb_fmc_adc_common_csr_fmc_status_pwr_good_i
wb_dat_i[31:0] wb_fmc_adc_common_csr_fmc_status_prst_i
wb_dat_o[31:0] wb_fmc_adc_common_csr_fmc_status_reserved_i[27:0]
wb_cyc_i  
wb_sel_i[3:0] Trigger control:
wb_stb_i wb_fmc_adc_common_csr_trigger_dir_o
wb_we_i wb_fmc_adc_common_csr_trigger_term_o
wb_ack_o wb_fmc_adc_common_csr_trigger_trig_val_o
wb_stall_o wb_fmc_adc_common_csr_trigger_reserved_i[28:0]
 
Monitor and FMC status control register:
wb_fmc_adc_common_csr_monitor_test_data_en_o
wb_fmc_adc_common_csr_monitor_led1_o
wb_fmc_adc_common_csr_monitor_led2_o
wb_fmc_adc_common_csr_monitor_led3_o
wb_fmc_adc_common_csr_monitor_reserved_i[27:0]

3. Register description

3.1. Status register

HW prefix: wb_fmc_adc_common_csr_fmc_status
HW address: 0x0
C prefix: FMC_STATUS
C offset: 0x0
31 30 29 28 27 26 25 24
- RESERVED[27:21]
23 22 21 20 19 18 17 16
RESERVED[20:13]
15 14 13 12 11 10 9 8
RESERVED[12:5]
7 6 5 4 3 2 1 0
RESERVED[4:0] PRST PWR_GOOD MMCM_LOCKED

3.2. Trigger control

HW prefix: wb_fmc_adc_common_csr_trigger
HW address: 0x1
C prefix: TRIGGER
C offset: 0x4
31 30 29 28 27 26 25 24
RESERVED[28:21]
23 22 21 20 19 18 17 16
RESERVED[20:13]
15 14 13 12 11 10 9 8
RESERVED[12:5]
7 6 5 4 3 2 1 0
RESERVED[4:0] TRIG_VAL TERM DIR

3.3. Monitor and FMC status control register

HW prefix: wb_fmc_adc_common_csr_monitor
HW address: 0x2
C prefix: MONITOR
C offset: 0x8
31 30 29 28 27 26 25 24
RESERVED[27:20]
23 22 21 20 19 18 17 16
RESERVED[19:12]
15 14 13 12 11 10 9 8
RESERVED[11:4]
7 6 5 4 3 2 1 0
RESERVED[3:0] LED3 LED2 LED1 TEST_DATA_EN