Simple Wishbone DMA interface for peripherals which want to stream data to a DMA
H/W Address | Type | Name | VHDL/Verilog prefix | C prefix |
---|---|---|---|---|
0x0 | REG | Control/Status register | dma_iface_ctl | CTL |
0x1 | REG | Transaction Counter | dma_iface_tr_cntr | TR_CNTR |
0x2 | FIFOREG | FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0 | dma_iface_fifo_c2b_r0 | FIFO_C2B_R0 |
0x3 | FIFOREG | FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1 | dma_iface_fifo_c2b_r1 | FIFO_C2B_R1 |
0x4 | REG | FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register | dma_iface_fifo_c2b_csr | FIFO_C2B_CSR |
0x5 | FIFOREG | FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0 | dma_iface_fifo_b2c_r0 | FIFO_B2C_R0 |
0x6 | REG | FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register | dma_iface_fifo_b2c_csr | FIFO_B2C_CSR |
→ | rst_n_i | Control/Status register: | ||
→ | clk_sys_i | dma_iface_ctl_start_o | → | |
⇒ | wb_adr_i[2:0] | dma_iface_ctl_done_i | ← | |
⇒ | wb_dat_i[31:0] | dma_iface_ctl_ovf_i | ← | |
⇐ | wb_dat_o[31:0] | |||
→ | wb_cyc_i | Transaction Counter: | ||
⇒ | wb_sel_i[3:0] | dma_iface_tr_cntr_o[31:0] | ⇒ | |
→ | wb_stb_i | |||
→ | wb_we_i | FIFO C2B (Core -> DMA) synchronization: | ||
← | wb_ack_o | dma_iface_fifo_c2b_wr_req_i | ← | |
← | wb_stall_o | dma_iface_fifo_c2b_wr_full_o | → | |
dma_iface_fifo_c2b_wr_empty_o | → | |||
dma_iface_fifo_c2b_wr_usedw_o[7:0] | ⇒ | |||
dma_iface_fifo_c2b_data_i[31:0] | ⇐ | |||
dma_iface_fifo_c2b_last_i | ← | |||
FIFO B2C (Bus -> Core) synchronization: | ||||
dma_iface_fifo_b2c_rd_req_i | ← | |||
dma_iface_fifo_b2c_rd_full_o | → | |||
dma_iface_fifo_b2c_rd_empty_o | → | |||
dma_iface_fifo_b2c_rd_usedw_o[7:0] | ⇒ | |||
dma_iface_fifo_b2c_data_o[31:0] | ⇒ | |||
FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0: | ||||
FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1: | ||||
FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0: |
HW prefix: | dma_iface_ctl |
HW address: | 0x0 |
C prefix: | CTL |
C offset: | 0x0 |
A register defining the Control and Status of the core.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | OVF | DONE | START |
HW prefix: | dma_iface_tr_cntr |
HW address: | 0x1 |
C prefix: | TR_CNTR |
C offset: | 0x4 |
Register holding the word count to be transfered to DMA
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
TR_CNTR[31:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
TR_CNTR[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
TR_CNTR[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
TR_CNTR[7:0] |
HW prefix: | dma_iface_fifo_c2b_r0 |
HW address: | 0x2 |
C prefix: | FIFO_C2B_R0 |
C offset: | 0x8 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
DATA[31:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
DATA[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
DATA[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
DATA[7:0] |
HW prefix: | dma_iface_fifo_c2b_r1 |
HW address: | 0x3 |
C prefix: | FIFO_C2B_R1 |
C offset: | 0xc |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | - | - |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
- | - | - | - | - | - | - | LAST |
HW prefix: | dma_iface_fifo_c2b_csr |
HW address: | 0x4 |
C prefix: | FIFO_C2B_CSR |
C offset: | 0x10 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | EMPTY | FULL |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
USEDW[7:0] |
HW prefix: | dma_iface_fifo_b2c_r0 |
HW address: | 0x5 |
C prefix: | FIFO_B2C_R0 |
C offset: | 0x14 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
DATA[31:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
DATA[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
DATA[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
DATA[7:0] |
HW prefix: | dma_iface_fifo_b2c_csr |
HW address: | 0x6 |
C prefix: | FIFO_B2C_CSR |
C offset: | 0x18 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
- | - | - | - | - | - | EMPTY | FULL |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
- | - | - | - | - | - | - | - |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
USEDW[7:0] |