acq_core_regs

BPM FSM Acquisition registers

Wishbone slave for BPM Core Acquisition

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Control register
3.2. Status register
3.3. Trigger configuration
3.4. Trigger data config threshold
3.5. Trigger data threshold
3.6. Trigger delay
3.7. Software trigger
3.8. Number of shots
3.9. Trigger address register
3.10. Pre-trigger samples
3.11. Post-trigger samples
3.12. Samples counter
3.13. DDR3 Start Address
3.14. DDR3 End Address
3.15. Acquisition channel control

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Control register acq_core_ctl CTL
0x1 REG Status register acq_core_sta STA
0x2 REG Trigger configuration acq_core_trig_cfg TRIG_CFG
0x3 REG Trigger data config threshold acq_core_trig_data_cfg TRIG_DATA_CFG
0x4 REG Trigger data threshold acq_core_trig_data_thres TRIG_DATA_THRES
0x5 REG Trigger delay acq_core_trig_dly TRIG_DLY
0x6 REG Software trigger acq_core_sw_trig SW_TRIG
0x7 REG Number of shots acq_core_shots SHOTS
0x8 REG Trigger address register acq_core_trig_pos TRIG_POS
0x9 REG Pre-trigger samples acq_core_pre_samples PRE_SAMPLES
0xa REG Post-trigger samples acq_core_post_samples POST_SAMPLES
0xb REG Samples counter acq_core_samples_cnt SAMPLES_CNT
0xc REG DDR3 Start Address acq_core_ddr3_start_addr DDR3_START_ADDR
0xd REG DDR3 End Address acq_core_ddr3_end_addr DDR3_END_ADDR
0xe REG Acquisition channel control acq_core_acq_chan_ctl ACQ_CHAN_CTL

2. HDL symbol

rst_n_i Control register:
clk_sys_i acq_core_ctl_fsm_start_acq_o
wb_adr_i[3:0] acq_core_ctl_fsm_stop_acq_o
wb_dat_i[31:0] acq_core_ctl_reserved1_o[13:0]
wb_dat_o[31:0] acq_core_ctl_fsm_acq_now_o
wb_cyc_i acq_core_ctl_reserved2_o[14:0]
wb_sel_i[3:0]  
wb_stb_i Status register:
wb_we_i acq_core_sta_fsm_state_i[2:0]
wb_ack_o acq_core_sta_fsm_acq_done_i
wb_stall_o acq_core_sta_reserved1_i[3:0]
acq_core_sta_fc_trans_done_i
acq_core_sta_fc_full_i
acq_core_sta_reserved2_i[5:0]
acq_core_sta_ddr3_trans_done_i
acq_core_sta_reserved3_i[14:0]
 
Trigger configuration:
acq_core_trig_cfg_hw_trig_sel_o
acq_core_trig_cfg_hw_trig_pol_o
acq_core_trig_cfg_hw_trig_en_o
acq_core_trig_cfg_sw_trig_en_o
acq_core_trig_cfg_int_trig_sel_o[4:0]
acq_core_trig_cfg_reserved_o[22:0]
 
Trigger data config threshold:
acq_core_trig_data_cfg_thres_filt_o[7:0]
acq_core_trig_data_cfg_reserved_o[23:0]
 
Trigger data threshold:
acq_core_trig_data_thres_o[31:0]
 
Trigger delay:
acq_core_trig_dly_o[31:0]
 
Software trigger:
acq_core_sw_trig_o[31:0]
acq_core_sw_trig_wr_o
 
Number of shots:
acq_core_shots_nb_o[15:0]
acq_core_shots_reserved_o[15:0]
 
Trigger address register:
acq_core_trig_pos_i[31:0]
 
Pre-trigger samples:
acq_core_pre_samples_o[31:0]
 
Post-trigger samples:
acq_core_post_samples_o[31:0]
 
Samples counter:
acq_core_samples_cnt_i[31:0]
 
DDR3 Start Address:
acq_core_ddr3_start_addr_o[31:0]
 
DDR3 End Address:
acq_core_ddr3_end_addr_o[31:0]
 
Acquisition channel control:
acq_core_acq_chan_ctl_which_o[4:0]
acq_core_acq_chan_ctl_reserved_o[2:0]
acq_core_acq_chan_ctl_dtrig_which_o[4:0]
acq_core_acq_chan_ctl_reserved1_o[18:0]

3. Register description

3.1. Control register

HW prefix: acq_core_ctl
HW address: 0x0
C prefix: CTL
C offset: 0x0
31 30 29 28 27 26 25 24
RESERVED2[14:7]
23 22 21 20 19 18 17 16
RESERVED2[6:0] FSM_ACQ_NOW
15 14 13 12 11 10 9 8
RESERVED1[13:6]
7 6 5 4 3 2 1 0
RESERVED1[5:0] FSM_STOP_ACQ FSM_START_ACQ

3.2. Status register

HW prefix: acq_core_sta
HW address: 0x1
C prefix: STA
C offset: 0x4
31 30 29 28 27 26 25 24
RESERVED3[14:7]
23 22 21 20 19 18 17 16
RESERVED3[6:0] DDR3_TRANS_DONE
15 14 13 12 11 10 9 8
RESERVED2[5:0] FC_FULL FC_TRANS_DONE
7 6 5 4 3 2 1 0
RESERVED1[3:0] FSM_ACQ_DONE FSM_STATE[2:0]

3.3. Trigger configuration

HW prefix: acq_core_trig_cfg
HW address: 0x2
C prefix: TRIG_CFG
C offset: 0x8
31 30 29 28 27 26 25 24
RESERVED[22:15]
23 22 21 20 19 18 17 16
RESERVED[14:7]
15 14 13 12 11 10 9 8
RESERVED[6:0] INT_TRIG_SEL[4:4]
7 6 5 4 3 2 1 0
INT_TRIG_SEL[3:0] SW_TRIG_EN HW_TRIG_EN HW_TRIG_POL HW_TRIG_SEL

3.4. Trigger data config threshold

HW prefix: acq_core_trig_data_cfg
HW address: 0x3
C prefix: TRIG_DATA_CFG
C offset: 0xc
31 30 29 28 27 26 25 24
RESERVED[23:16]
23 22 21 20 19 18 17 16
RESERVED[15:8]
15 14 13 12 11 10 9 8
RESERVED[7:0]
7 6 5 4 3 2 1 0
THRES_FILT[7:0]

3.5. Trigger data threshold

HW prefix: acq_core_trig_data_thres
HW address: 0x4
C prefix: TRIG_DATA_THRES
C offset: 0x10
31 30 29 28 27 26 25 24
TRIG_DATA_THRES[31:24]
23 22 21 20 19 18 17 16
TRIG_DATA_THRES[23:16]
15 14 13 12 11 10 9 8
TRIG_DATA_THRES[15:8]
7 6 5 4 3 2 1 0
TRIG_DATA_THRES[7:0]

3.6. Trigger delay

HW prefix: acq_core_trig_dly
HW address: 0x5
C prefix: TRIG_DLY
C offset: 0x14
31 30 29 28 27 26 25 24
TRIG_DLY[31:24]
23 22 21 20 19 18 17 16
TRIG_DLY[23:16]
15 14 13 12 11 10 9 8
TRIG_DLY[15:8]
7 6 5 4 3 2 1 0
TRIG_DLY[7:0]

3.7. Software trigger

HW prefix: acq_core_sw_trig
HW address: 0x6
C prefix: SW_TRIG
C offset: 0x18

Writing (anything) to this register generates a software trigger.

31 30 29 28 27 26 25 24
SW_TRIG[31:24]
23 22 21 20 19 18 17 16
SW_TRIG[23:16]
15 14 13 12 11 10 9 8
SW_TRIG[15:8]
7 6 5 4 3 2 1 0
SW_TRIG[7:0]

3.8. Number of shots

HW prefix: acq_core_shots
HW address: 0x7
C prefix: SHOTS
C offset: 0x1c
31 30 29 28 27 26 25 24
RESERVED[15:8]
23 22 21 20 19 18 17 16
RESERVED[7:0]
15 14 13 12 11 10 9 8
NB[15:8]
7 6 5 4 3 2 1 0
NB[7:0]

3.9. Trigger address register

HW prefix: acq_core_trig_pos
HW address: 0x8
C prefix: TRIG_POS
C offset: 0x20
31 30 29 28 27 26 25 24
TRIG_POS[31:24]
23 22 21 20 19 18 17 16
TRIG_POS[23:16]
15 14 13 12 11 10 9 8
TRIG_POS[15:8]
7 6 5 4 3 2 1 0
TRIG_POS[7:0]

3.10. Pre-trigger samples

HW prefix: acq_core_pre_samples
HW address: 0x9
C prefix: PRE_SAMPLES
C offset: 0x24
31 30 29 28 27 26 25 24
PRE_SAMPLES[31:24]
23 22 21 20 19 18 17 16
PRE_SAMPLES[23:16]
15 14 13 12 11 10 9 8
PRE_SAMPLES[15:8]
7 6 5 4 3 2 1 0
PRE_SAMPLES[7:0]

3.11. Post-trigger samples

HW prefix: acq_core_post_samples
HW address: 0xa
C prefix: POST_SAMPLES
C offset: 0x28
31 30 29 28 27 26 25 24
POST_SAMPLES[31:24]
23 22 21 20 19 18 17 16
POST_SAMPLES[23:16]
15 14 13 12 11 10 9 8
POST_SAMPLES[15:8]
7 6 5 4 3 2 1 0
POST_SAMPLES[7:0]

3.12. Samples counter

HW prefix: acq_core_samples_cnt
HW address: 0xb
C prefix: SAMPLES_CNT
C offset: 0x2c
31 30 29 28 27 26 25 24
SAMPLES_CNT[31:24]
23 22 21 20 19 18 17 16
SAMPLES_CNT[23:16]
15 14 13 12 11 10 9 8
SAMPLES_CNT[15:8]
7 6 5 4 3 2 1 0
SAMPLES_CNT[7:0]

3.13. DDR3 Start Address

HW prefix: acq_core_ddr3_start_addr
HW address: 0xc
C prefix: DDR3_START_ADDR
C offset: 0x30
31 30 29 28 27 26 25 24
DDR3_START_ADDR[31:24]
23 22 21 20 19 18 17 16
DDR3_START_ADDR[23:16]
15 14 13 12 11 10 9 8
DDR3_START_ADDR[15:8]
7 6 5 4 3 2 1 0
DDR3_START_ADDR[7:0]

3.14. DDR3 End Address

HW prefix: acq_core_ddr3_end_addr
HW address: 0xd
C prefix: DDR3_END_ADDR
C offset: 0x34
31 30 29 28 27 26 25 24
DDR3_END_ADDR[31:24]
23 22 21 20 19 18 17 16
DDR3_END_ADDR[23:16]
15 14 13 12 11 10 9 8
DDR3_END_ADDR[15:8]
7 6 5 4 3 2 1 0
DDR3_END_ADDR[7:0]

3.15. Acquisition channel control

HW prefix: acq_core_acq_chan_ctl
HW address: 0xe
C prefix: ACQ_CHAN_CTL
C offset: 0x38
31 30 29 28 27 26 25 24
RESERVED1[18:11]
23 22 21 20 19 18 17 16
RESERVED1[10:3]
15 14 13 12 11 10 9 8
RESERVED1[2:0] DTRIG_WHICH[4:0]
7 6 5 4 3 2 1 0
RESERVED[2:0] WHICH[4:0]