wb_fmc516_regs

FMC ADC 250MS/s core registers

Wishbone slave for FMC ADC 250MS/s core

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Status register
3.2. Control register
3.3. Trigger configuration
3.4. Global ADC Status register
3.5. Global ADC Control register
3.6. Channel 0 status register
3.7. Channel 0 fine delay register
3.8. Channel 0 coarse delay register
3.9. Channel 1 status register
3.10. Channel 1 fine delay register
3.11. Channel 1 coarse delay register
3.12. Channel 2 status register
3.13. Channel 2 fine delay register
3.14. Channel 2 coarse delay register
3.15. Channel 3 status register
3.16. Channel 3 fine delay register
3.17. Channel 3 coarse delay register

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Status register fmc516_fmc_sta FMC_STA
0x1 REG Control register fmc516_fmc_ctl FMC_CTL
0x2 REG Trigger configuration fmc516_trig_cfg TRIG_CFG
0x3 REG Global ADC Status register fmc516_adc_sta ADC_STA
0x4 REG Global ADC Control register fmc516_adc_ctl ADC_CTL
0x5 REG Channel 0 status register fmc516_ch0_sta CH0_STA
0x6 REG Channel 0 fine delay register fmc516_ch0_fn_dly CH0_FN_DLY
0x7 REG Channel 0 coarse delay register fmc516_ch0_cs_dly CH0_CS_DLY
0x8 REG Channel 1 status register fmc516_ch1_sta CH1_STA
0x9 REG Channel 1 fine delay register fmc516_ch1_fn_dly CH1_FN_DLY
0xa REG Channel 1 coarse delay register fmc516_ch1_cs_dly CH1_CS_DLY
0xb REG Channel 2 status register fmc516_ch2_sta CH2_STA
0xc REG Channel 2 fine delay register fmc516_ch2_fn_dly CH2_FN_DLY
0xd REG Channel 2 coarse delay register fmc516_ch2_cs_dly CH2_CS_DLY
0xe REG Channel 3 status register fmc516_ch3_sta CH3_STA
0xf REG Channel 3 fine delay register fmc516_ch3_fn_dly CH3_FN_DLY
0x10 REG Channel 3 coarse delay register fmc516_ch3_cs_dly CH3_CS_DLY

2. HDL symbol

rst_n_i Status register:
clk_sys_i fmc516_fmc_sta_lmk_locked_i
wb_adr_i[4:0] fmc516_fmc_sta_mmcm_locked_i
wb_dat_i[31:0] fmc516_fmc_sta_pwr_good_i
wb_dat_o[31:0] fmc516_fmc_sta_prst_i
wb_cyc_i fmc516_fmc_sta_reserved_i[27:0]
wb_sel_i[3:0]  
wb_stb_i Control register:
wb_we_i fmc516_fmc_ctl_test_data_en_o
wb_ack_o fmc516_fmc_ctl_led_0_o
wb_stall_o fmc516_fmc_ctl_led_1_o
fmc516_fmc_ctl_clk_sel_o
fmc516_fmc_ctl_vcxo_out_en_o
fmc516_fmc_ctl_reserved_o[26:0]
 
Trigger configuration:
fmc516_trig_cfg_hw_trig_pol_o
fmc516_trig_cfg_hw_trig_en_o
fmc516_trig_cfg_reserved_o[29:0]
 
Global ADC Status register:
fmc516_adc_sta_clk_chains_i[3:0]
fmc516_adc_sta_reserved_clk_chains_i[3:0]
fmc516_adc_sta_data_chains_i[3:0]
fmc516_adc_sta_reserved_data_chains_i[3:0]
fmc516_adc_sta_adc_pkt_size_i[15:0]
 
Global ADC Control register:
fmc516_adc_ctl_update_clk_dly_o
fmc516_adc_ctl_update_data_dly_o
fmc516_adc_ctl_rst_adcs_o
fmc516_adc_ctl_rst_div_adcs_o
fmc516_adc_ctl_reserved_i[27:0]
 
Channel 0 status register:
fmc516_ch0_sta_val_i[15:0]
fmc516_ch0_sta_reserved_i[15:0]
 
Channel 0 fine delay register:
fmc516_ch0_fn_dly_clk_chain_dly_o[4:0]
fmc516_ch0_fn_dly_clk_chain_dly_i[4:0]
fmc516_ch0_fn_dly_clk_chain_dly_load_o
fmc516_ch0_fn_dly_reserved_clk_chain_dly_i[2:0]
fmc516_ch0_fn_dly_data_chain_dly_o[4:0]
fmc516_ch0_fn_dly_data_chain_dly_i[4:0]
fmc516_ch0_fn_dly_data_chain_dly_load_o
fmc516_ch0_fn_dly_reserved_data_chain_dly_i[2:0]
fmc516_ch0_fn_dly_inc_clk_chain_dly_o
fmc516_ch0_fn_dly_dec_clk_chain_dly_o
fmc516_ch0_fn_dly_reserved_clk_incdec_dly_o[5:0]
fmc516_ch0_fn_dly_inc_data_chain_dly_o
fmc516_ch0_fn_dly_dec_data_chain_dly_o
fmc516_ch0_fn_dly_reserved_data_incdec_dly_o[5:0]
 
Channel 0 coarse delay register:
fmc516_ch0_cs_dly_fe_dly_o[1:0]
fmc516_ch0_cs_dly_reserved_fe_dly_o[5:0]
fmc516_ch0_cs_dly_rg_dly_o[1:0]
fmc516_ch0_cs_dly_reserved_rg_dly_o[21:0]
 
Channel 1 status register:
fmc516_ch1_sta_val_i[15:0]
fmc516_ch1_sta_reserved_i[15:0]
 
Channel 1 fine delay register:
fmc516_ch1_fn_dly_clk_chain_dly_o[4:0]
fmc516_ch1_fn_dly_clk_chain_dly_i[4:0]
fmc516_ch1_fn_dly_clk_chain_dly_load_o
fmc516_ch1_fn_dly_reserved_clk_chain_dly_i[2:0]
fmc516_ch1_fn_dly_data_chain_dly_o[4:0]
fmc516_ch1_fn_dly_data_chain_dly_i[4:0]
fmc516_ch1_fn_dly_data_chain_dly_load_o
fmc516_ch1_fn_dly_reserved_data_chain_dly_i[2:0]
fmc516_ch1_fn_dly_inc_clk_chain_dly_o
fmc516_ch1_fn_dly_dec_clk_chain_dly_o
fmc516_ch1_fn_dly_reserved_clk_incdec_dly_o[5:0]
fmc516_ch1_fn_dly_inc_data_chain_dly_o
fmc516_ch1_fn_dly_dec_data_chain_dly_o
fmc516_ch1_fn_dly_reserved_data_incdec_dly_o[5:0]
 
Channel 1 coarse delay register:
fmc516_ch1_cs_dly_fe_dly_o[1:0]
fmc516_ch1_cs_dly_reserved_fe_dly_o[5:0]
fmc516_ch1_cs_dly_rg_dly_o[1:0]
fmc516_ch1_cs_dly_reserved_rg_dly_o[21:0]
 
Channel 2 status register:
fmc516_ch2_sta_val_i[15:0]
fmc516_ch2_sta_reserved_i[15:0]
 
Channel 2 fine delay register:
fmc516_ch2_fn_dly_clk_chain_dly_o[4:0]
fmc516_ch2_fn_dly_clk_chain_dly_i[4:0]
fmc516_ch2_fn_dly_clk_chain_dly_load_o
fmc516_ch2_fn_dly_reserved_clk_chain_dly_i[2:0]
fmc516_ch2_fn_dly_data_chain_dly_o[4:0]
fmc516_ch2_fn_dly_data_chain_dly_i[4:0]
fmc516_ch2_fn_dly_data_chain_dly_load_o
fmc516_ch2_fn_dly_reserved_data_chain_dly_i[2:0]
fmc516_ch2_fn_dly_inc_clk_chain_dly_o
fmc516_ch2_fn_dly_dec_clk_chain_dly_o
fmc516_ch2_fn_dly_reserved_clk_incdec_dly_o[5:0]
fmc516_ch2_fn_dly_inc_data_chain_dly_o
fmc516_ch2_fn_dly_dec_data_chain_dly_o
fmc516_ch2_fn_dly_reserved_data_incdec_dly_o[5:0]
 
Channel 2 coarse delay register:
fmc516_ch2_cs_dly_fe_dly_o[1:0]
fmc516_ch2_cs_dly_reserved_fe_dly_o[5:0]
fmc516_ch2_cs_dly_rg_dly_o[1:0]
fmc516_ch2_cs_dly_reserved_rg_dly_o[21:0]
 
Channel 3 status register:
fmc516_ch3_sta_val_i[15:0]
fmc516_ch3_sta_reserved_i[15:0]
 
Channel 3 fine delay register:
fmc516_ch3_fn_dly_clk_chain_dly_o[4:0]
fmc516_ch3_fn_dly_clk_chain_dly_i[4:0]
fmc516_ch3_fn_dly_clk_chain_dly_load_o
fmc516_ch3_fn_dly_reserved_clk_chain_dly_i[2:0]
fmc516_ch3_fn_dly_data_chain_dly_o[4:0]
fmc516_ch3_fn_dly_data_chain_dly_i[4:0]
fmc516_ch3_fn_dly_data_chain_dly_load_o
fmc516_ch3_fn_dly_reserved_data_chain_dly_i[2:0]
fmc516_ch3_fn_dly_inc_clk_chain_dly_o
fmc516_ch3_fn_dly_dec_clk_chain_dly_o
fmc516_ch3_fn_dly_reserved_clk_incdec_dly_o[5:0]
fmc516_ch3_fn_dly_inc_data_chain_dly_o
fmc516_ch3_fn_dly_dec_data_chain_dly_o
fmc516_ch3_fn_dly_reserved_data_incdec_dly_o[5:0]
 
Channel 3 coarse delay register:
fmc516_ch3_cs_dly_fe_dly_o[1:0]
fmc516_ch3_cs_dly_reserved_fe_dly_o[5:0]
fmc516_ch3_cs_dly_rg_dly_o[1:0]
fmc516_ch3_cs_dly_reserved_rg_dly_o[21:0]

3. Register description

3.1. Status register

HW prefix: fmc516_fmc_sta
HW address: 0x0
C prefix: FMC_STA
C offset: 0x0
31 30 29 28 27 26 25 24
RESERVED[27:20]
23 22 21 20 19 18 17 16
RESERVED[19:12]
15 14 13 12 11 10 9 8
RESERVED[11:4]
7 6 5 4 3 2 1 0
RESERVED[3:0] PRST PWR_GOOD MMCM_LOCKED LMK_LOCKED

3.2. Control register

HW prefix: fmc516_fmc_ctl
HW address: 0x1
C prefix: FMC_CTL
C offset: 0x4
31 30 29 28 27 26 25 24
RESERVED[26:19]
23 22 21 20 19 18 17 16
RESERVED[18:11]
15 14 13 12 11 10 9 8
RESERVED[10:3]
7 6 5 4 3 2 1 0
RESERVED[2:0] VCXO_OUT_EN CLK_SEL LED_1 LED_0 TEST_DATA_EN

3.3. Trigger configuration

HW prefix: fmc516_trig_cfg
HW address: 0x2
C prefix: TRIG_CFG
C offset: 0x8
31 30 29 28 27 26 25 24
RESERVED[29:22]
23 22 21 20 19 18 17 16
RESERVED[21:14]
15 14 13 12 11 10 9 8
RESERVED[13:6]
7 6 5 4 3 2 1 0
RESERVED[5:0] HW_TRIG_EN HW_TRIG_POL

3.4. Global ADC Status register

HW prefix: fmc516_adc_sta
HW address: 0x3
C prefix: ADC_STA
C offset: 0xc

Global ADC status register.

31 30 29 28 27 26 25 24
ADC_PKT_SIZE[15:8]
23 22 21 20 19 18 17 16
ADC_PKT_SIZE[7:0]
15 14 13 12 11 10 9 8
RESERVED_DATA_CHAINS[3:0] DATA_CHAINS[3:0]
7 6 5 4 3 2 1 0
RESERVED_CLK_CHAINS[3:0] CLK_CHAINS[3:0]

3.5. Global ADC Control register

HW prefix: fmc516_adc_ctl
HW address: 0x4
C prefix: ADC_CTL
C offset: 0x10

Global ADC control register.

31 30 29 28 27 26 25 24
RESERVED[27:20]
23 22 21 20 19 18 17 16
RESERVED[19:12]
15 14 13 12 11 10 9 8
RESERVED[11:4]
7 6 5 4 3 2 1 0
RESERVED[3:0] RST_DIV_ADCS RST_ADCS UPDATE_DATA_DLY UPDATE_CLK_DLY

3.6. Channel 0 status register

HW prefix: fmc516_ch0_sta
HW address: 0x5
C prefix: CH0_STA
C offset: 0x14
31 30 29 28 27 26 25 24
RESERVED[15:8]
23 22 21 20 19 18 17 16
RESERVED[7:0]
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.7. Channel 0 fine delay register

HW prefix: fmc516_ch0_fn_dly
HW address: 0x6
C prefix: CH0_FN_DLY
C offset: 0x18
31 30 29 28 27 26 25 24
RESERVED_DATA_INCDEC_DLY[5:0] DEC_DATA_CHAIN_DLY INC_DATA_CHAIN_DLY
23 22 21 20 19 18 17 16
RESERVED_CLK_INCDEC_DLY[5:0] DEC_CLK_CHAIN_DLY INC_CLK_CHAIN_DLY
15 14 13 12 11 10 9 8
RESERVED_DATA_CHAIN_DLY[2:0] DATA_CHAIN_DLY[4:0]
7 6 5 4 3 2 1 0
RESERVED_CLK_CHAIN_DLY[2:0] CLK_CHAIN_DLY[4:0]

3.8. Channel 0 coarse delay register

HW prefix: fmc516_ch0_cs_dly
HW address: 0x7
C prefix: CH0_CS_DLY
C offset: 0x1c
31 30 29 28 27 26 25 24
RESERVED_RG_DLY[21:14]
23 22 21 20 19 18 17 16
RESERVED_RG_DLY[13:6]
15 14 13 12 11 10 9 8
RESERVED_RG_DLY[5:0] RG_DLY[1:0]
7 6 5 4 3 2 1 0
RESERVED_FE_DLY[5:0] FE_DLY[1:0]

3.9. Channel 1 status register

HW prefix: fmc516_ch1_sta
HW address: 0x8
C prefix: CH1_STA
C offset: 0x20
31 30 29 28 27 26 25 24
RESERVED[15:8]
23 22 21 20 19 18 17 16
RESERVED[7:0]
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.10. Channel 1 fine delay register

HW prefix: fmc516_ch1_fn_dly
HW address: 0x9
C prefix: CH1_FN_DLY
C offset: 0x24
31 30 29 28 27 26 25 24
RESERVED_DATA_INCDEC_DLY[5:0] DEC_DATA_CHAIN_DLY INC_DATA_CHAIN_DLY
23 22 21 20 19 18 17 16
RESERVED_CLK_INCDEC_DLY[5:0] DEC_CLK_CHAIN_DLY INC_CLK_CHAIN_DLY
15 14 13 12 11 10 9 8
RESERVED_DATA_CHAIN_DLY[2:0] DATA_CHAIN_DLY[4:0]
7 6 5 4 3 2 1 0
RESERVED_CLK_CHAIN_DLY[2:0] CLK_CHAIN_DLY[4:0]

3.11. Channel 1 coarse delay register

HW prefix: fmc516_ch1_cs_dly
HW address: 0xa
C prefix: CH1_CS_DLY
C offset: 0x28
31 30 29 28 27 26 25 24
RESERVED_RG_DLY[21:14]
23 22 21 20 19 18 17 16
RESERVED_RG_DLY[13:6]
15 14 13 12 11 10 9 8
RESERVED_RG_DLY[5:0] RG_DLY[1:0]
7 6 5 4 3 2 1 0
RESERVED_FE_DLY[5:0] FE_DLY[1:0]

3.12. Channel 2 status register

HW prefix: fmc516_ch2_sta
HW address: 0xb
C prefix: CH2_STA
C offset: 0x2c
31 30 29 28 27 26 25 24
RESERVED[15:8]
23 22 21 20 19 18 17 16
RESERVED[7:0]
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.13. Channel 2 fine delay register

HW prefix: fmc516_ch2_fn_dly
HW address: 0xc
C prefix: CH2_FN_DLY
C offset: 0x30
31 30 29 28 27 26 25 24
RESERVED_DATA_INCDEC_DLY[5:0] DEC_DATA_CHAIN_DLY INC_DATA_CHAIN_DLY
23 22 21 20 19 18 17 16
RESERVED_CLK_INCDEC_DLY[5:0] DEC_CLK_CHAIN_DLY INC_CLK_CHAIN_DLY
15 14 13 12 11 10 9 8
RESERVED_DATA_CHAIN_DLY[2:0] DATA_CHAIN_DLY[4:0]
7 6 5 4 3 2 1 0
RESERVED_CLK_CHAIN_DLY[2:0] CLK_CHAIN_DLY[4:0]

3.14. Channel 2 coarse delay register

HW prefix: fmc516_ch2_cs_dly
HW address: 0xd
C prefix: CH2_CS_DLY
C offset: 0x34
31 30 29 28 27 26 25 24
RESERVED_RG_DLY[21:14]
23 22 21 20 19 18 17 16
RESERVED_RG_DLY[13:6]
15 14 13 12 11 10 9 8
RESERVED_RG_DLY[5:0] RG_DLY[1:0]
7 6 5 4 3 2 1 0
RESERVED_FE_DLY[5:0] FE_DLY[1:0]

3.15. Channel 3 status register

HW prefix: fmc516_ch3_sta
HW address: 0xe
C prefix: CH3_STA
C offset: 0x38
31 30 29 28 27 26 25 24
RESERVED[15:8]
23 22 21 20 19 18 17 16
RESERVED[7:0]
15 14 13 12 11 10 9 8
VAL[15:8]
7 6 5 4 3 2 1 0
VAL[7:0]

3.16. Channel 3 fine delay register

HW prefix: fmc516_ch3_fn_dly
HW address: 0xf
C prefix: CH3_FN_DLY
C offset: 0x3c
31 30 29 28 27 26 25 24
RESERVED_DATA_INCDEC_DLY[5:0] DEC_DATA_CHAIN_DLY INC_DATA_CHAIN_DLY
23 22 21 20 19 18 17 16
RESERVED_CLK_INCDEC_DLY[5:0] DEC_CLK_CHAIN_DLY INC_CLK_CHAIN_DLY
15 14 13 12 11 10 9 8
RESERVED_DATA_CHAIN_DLY[2:0] DATA_CHAIN_DLY[4:0]
7 6 5 4 3 2 1 0
RESERVED_CLK_CHAIN_DLY[2:0] CLK_CHAIN_DLY[4:0]

3.17. Channel 3 coarse delay register

HW prefix: fmc516_ch3_cs_dly
HW address: 0x10
C prefix: CH3_CS_DLY
C offset: 0x40
31 30 29 28 27 26 25 24
RESERVED_RG_DLY[21:14]
23 22 21 20 19 18 17 16
RESERVED_RG_DLY[13:6]
15 14 13 12 11 10 9 8
RESERVED_RG_DLY[5:0] RG_DLY[1:0]
7 6 5 4 3 2 1 0
RESERVED_FE_DLY[5:0] FE_DLY[1:0]