wb_dma_ctl_iface

Wishbone DMA Streaming Control Interface

Simple Wishbone DMA interface for controlling the DMA Streaming peripheral

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Control/Status register
3.2. Transaction Counter

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Control/Status register dma_ctl_iface_ctl CTL
0x1 REG Transaction Counter dma_ctl_iface_tr_cntr TR_CNTR

2. HDL symbol

rst_n_i Control/Status register:
clk_sys_i dma_ctl_iface_ctl_start_o
wb_adr_i dma_ctl_iface_ctl_done_i
wb_dat_i[31:0] dma_ctl_iface_ctl_ovf_i
wb_dat_o[31:0]  
wb_cyc_i Transaction Counter:
wb_sel_i[3:0] dma_ctl_iface_tr_cntr_o[31:0]
wb_stb_i
wb_we_i
wb_ack_o
wb_stall_o

3. Register description

3.1. Control/Status register

HW prefix: dma_ctl_iface_ctl
HW address: 0x0
C prefix: CTL
C offset: 0x0

A register defining the Control and Status of the core.

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - OVF DONE START

3.2. Transaction Counter

HW prefix: dma_ctl_iface_tr_cntr
HW address: 0x1
C prefix: TR_CNTR
C offset: 0x4

Register holding the word count to be transfered to DMA

31 30 29 28 27 26 25 24
TR_CNTR[31:24]
23 22 21 20 19 18 17 16
TR_CNTR[23:16]
15 14 13 12 11 10 9 8
TR_CNTR[15:8]
7 6 5 4 3 2 1 0
TR_CNTR[7:0]