wb_trigger_iface_regs

Control and status register for the MLVDS trigger

Wishbone slave for control and status registers related to the MLVDS trigger

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Channel 0 Control
3.2. Channel 0 Configuration Parameters
3.3. Channel 0 Transmitter/Receiver Pulses Counter
3.4. Channel 1 Control
3.5. Channel 1 Configuration Parameters
3.6. Channel 1 Transmitter/Receiver Pulses Counter
3.7. Channel 2 Control
3.8. Channel 2 Configuration Parameters
3.9. Channel 2 Transmitter/Receiver Pulses Counter
3.10. Channel 3 Control
3.11. Channel 3 Configuration Parameters
3.12. Channel 3 Transmitter/Receiver Pulses Counter
3.13. Channel 4 Control
3.14. Channel 4 Configuration Parameters
3.15. Channel 4 Transmitter/Receiver Pulses Counter
3.16. Channel 5 Control
3.17. Channel 5 Configuration Parameters
3.18. Channel 5 Transmitter/Receiver Pulses Counter
3.19. Channel 6 Control
3.20. Channel 6 Configuration Parameters
3.21. Channel 6 Transmitter/Receiver Pulses Counter
3.22. Channel 7 Control
3.23. Channel 7 Configuration Parameters
3.24. Channel 7 Transmitter/Receiver Pulses Counter
3.25. Channel 8 Control
3.26. Channel 8 Configuration Parameters
3.27. Channel 8 Transmitter/Receiver Pulses Counter
3.28. Channel 9 Control
3.29. Channel 9 Configuration Parameters
3.30. Channel 9 Transmitter/Receiver Pulses Counter
3.31. Channel 10 Control
3.32. Channel 10 Configuration Parameters
3.33. Channel 10 Transmitter/Receiver Pulses Counter
3.34. Channel 11 Control
3.35. Channel 11 Configuration Parameters
3.36. Channel 11 Transmitter/Receiver Pulses Counter
3.37. Channel 12 Control
3.38. Channel 12 Configuration Parameters
3.39. Channel 12 Transmitter/Receiver Pulses Counter
3.40. Channel 13 Control
3.41. Channel 13 Configuration Parameters
3.42. Channel 13 Transmitter/Receiver Pulses Counter
3.43. Channel 14 Control
3.44. Channel 14 Configuration Parameters
3.45. Channel 14 Transmitter/Receiver Pulses Counter
3.46. Channel 15 Control
3.47. Channel 15 Configuration Parameters
3.48. Channel 15 Transmitter/Receiver Pulses Counter
3.49. Channel 16 Control
3.50. Channel 16 Configuration Parameters
3.51. Channel 16 Transmitter/Receiver Pulses Counter
3.52. Channel 17 Control
3.53. Channel 17 Configuration Parameters
3.54. Channel 17 Transmitter/Receiver Pulses Counter
3.55. Channel 18 Control
3.56. Channel 18 Configuration Parameters
3.57. Channel 18 Transmitter/Receiver Pulses Counter
3.58. Channel 19 Control
3.59. Channel 19 Configuration Parameters
3.60. Channel 19 Transmitter/Receiver Pulses Counter
3.61. Channel 20 Control
3.62. Channel 20 Configuration Parameters
3.63. Channel 20 Transmitter/Receiver Pulses Counter
3.64. Channel 21 Control
3.65. Channel 21 Configuration Parameters
3.66. Channel 21 Transmitter/Receiver Pulses Counter
3.67. Channel 22 Control
3.68. Channel 22 Configuration Parameters
3.69. Channel 22 Transmitter/Receiver Pulses Counter
3.70. Channel 23 Control
3.71. Channel 23 Configuration Parameters
3.72. Channel 23 Transmitter/Receiver Pulses Counter

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Channel 0 Control wb_trig_iface_ch0_ctl CH0_CTL
0x1 REG Channel 0 Configuration Parameters wb_trig_iface_ch0_cfg CH0_CFG
0x2 REG Channel 0 Transmitter/Receiver Pulses Counter wb_trig_iface_ch0_count CH0_COUNT
0x3 REG Channel 1 Control wb_trig_iface_ch1_ctl CH1_CTL
0x4 REG Channel 1 Configuration Parameters wb_trig_iface_ch1_cfg CH1_CFG
0x5 REG Channel 1 Transmitter/Receiver Pulses Counter wb_trig_iface_ch1_count CH1_COUNT
0x6 REG Channel 2 Control wb_trig_iface_ch2_ctl CH2_CTL
0x7 REG Channel 2 Configuration Parameters wb_trig_iface_ch2_cfg CH2_CFG
0x8 REG Channel 2 Transmitter/Receiver Pulses Counter wb_trig_iface_ch2_count CH2_COUNT
0x9 REG Channel 3 Control wb_trig_iface_ch3_ctl CH3_CTL
0xa REG Channel 3 Configuration Parameters wb_trig_iface_ch3_cfg CH3_CFG
0xb REG Channel 3 Transmitter/Receiver Pulses Counter wb_trig_iface_ch3_count CH3_COUNT
0xc REG Channel 4 Control wb_trig_iface_ch4_ctl CH4_CTL
0xd REG Channel 4 Configuration Parameters wb_trig_iface_ch4_cfg CH4_CFG
0xe REG Channel 4 Transmitter/Receiver Pulses Counter wb_trig_iface_ch4_count CH4_COUNT
0xf REG Channel 5 Control wb_trig_iface_ch5_ctl CH5_CTL
0x10 REG Channel 5 Configuration Parameters wb_trig_iface_ch5_cfg CH5_CFG
0x11 REG Channel 5 Transmitter/Receiver Pulses Counter wb_trig_iface_ch5_count CH5_COUNT
0x12 REG Channel 6 Control wb_trig_iface_ch6_ctl CH6_CTL
0x13 REG Channel 6 Configuration Parameters wb_trig_iface_ch6_cfg CH6_CFG
0x14 REG Channel 6 Transmitter/Receiver Pulses Counter wb_trig_iface_ch6_count CH6_COUNT
0x15 REG Channel 7 Control wb_trig_iface_ch7_ctl CH7_CTL
0x16 REG Channel 7 Configuration Parameters wb_trig_iface_ch7_cfg CH7_CFG
0x17 REG Channel 7 Transmitter/Receiver Pulses Counter wb_trig_iface_ch7_count CH7_COUNT
0x18 REG Channel 8 Control wb_trig_iface_ch8_ctl CH8_CTL
0x19 REG Channel 8 Configuration Parameters wb_trig_iface_ch8_cfg CH8_CFG
0x1a REG Channel 8 Transmitter/Receiver Pulses Counter wb_trig_iface_ch8_count CH8_COUNT
0x1b REG Channel 9 Control wb_trig_iface_ch9_ctl CH9_CTL
0x1c REG Channel 9 Configuration Parameters wb_trig_iface_ch9_cfg CH9_CFG
0x1d REG Channel 9 Transmitter/Receiver Pulses Counter wb_trig_iface_ch9_count CH9_COUNT
0x1e REG Channel 10 Control wb_trig_iface_ch10_ctl CH10_CTL
0x1f REG Channel 10 Configuration Parameters wb_trig_iface_ch10_cfg CH10_CFG
0x20 REG Channel 10 Transmitter/Receiver Pulses Counter wb_trig_iface_ch10_count CH10_COUNT
0x21 REG Channel 11 Control wb_trig_iface_ch11_ctl CH11_CTL
0x22 REG Channel 11 Configuration Parameters wb_trig_iface_ch11_cfg CH11_CFG
0x23 REG Channel 11 Transmitter/Receiver Pulses Counter wb_trig_iface_ch11_count CH11_COUNT
0x24 REG Channel 12 Control wb_trig_iface_ch12_ctl CH12_CTL
0x25 REG Channel 12 Configuration Parameters wb_trig_iface_ch12_cfg CH12_CFG
0x26 REG Channel 12 Transmitter/Receiver Pulses Counter wb_trig_iface_ch12_count CH12_COUNT
0x27 REG Channel 13 Control wb_trig_iface_ch13_ctl CH13_CTL
0x28 REG Channel 13 Configuration Parameters wb_trig_iface_ch13_cfg CH13_CFG
0x29 REG Channel 13 Transmitter/Receiver Pulses Counter wb_trig_iface_ch13_count CH13_COUNT
0x2a REG Channel 14 Control wb_trig_iface_ch14_ctl CH14_CTL
0x2b REG Channel 14 Configuration Parameters wb_trig_iface_ch14_cfg CH14_CFG
0x2c REG Channel 14 Transmitter/Receiver Pulses Counter wb_trig_iface_ch14_count CH14_COUNT
0x2d REG Channel 15 Control wb_trig_iface_ch15_ctl CH15_CTL
0x2e REG Channel 15 Configuration Parameters wb_trig_iface_ch15_cfg CH15_CFG
0x2f REG Channel 15 Transmitter/Receiver Pulses Counter wb_trig_iface_ch15_count CH15_COUNT
0x30 REG Channel 16 Control wb_trig_iface_ch16_ctl CH16_CTL
0x31 REG Channel 16 Configuration Parameters wb_trig_iface_ch16_cfg CH16_CFG
0x32 REG Channel 16 Transmitter/Receiver Pulses Counter wb_trig_iface_ch16_count CH16_COUNT
0x33 REG Channel 17 Control wb_trig_iface_ch17_ctl CH17_CTL
0x34 REG Channel 17 Configuration Parameters wb_trig_iface_ch17_cfg CH17_CFG
0x35 REG Channel 17 Transmitter/Receiver Pulses Counter wb_trig_iface_ch17_count CH17_COUNT
0x36 REG Channel 18 Control wb_trig_iface_ch18_ctl CH18_CTL
0x37 REG Channel 18 Configuration Parameters wb_trig_iface_ch18_cfg CH18_CFG
0x38 REG Channel 18 Transmitter/Receiver Pulses Counter wb_trig_iface_ch18_count CH18_COUNT
0x39 REG Channel 19 Control wb_trig_iface_ch19_ctl CH19_CTL
0x3a REG Channel 19 Configuration Parameters wb_trig_iface_ch19_cfg CH19_CFG
0x3b REG Channel 19 Transmitter/Receiver Pulses Counter wb_trig_iface_ch19_count CH19_COUNT
0x3c REG Channel 20 Control wb_trig_iface_ch20_ctl CH20_CTL
0x3d REG Channel 20 Configuration Parameters wb_trig_iface_ch20_cfg CH20_CFG
0x3e REG Channel 20 Transmitter/Receiver Pulses Counter wb_trig_iface_ch20_count CH20_COUNT
0x3f REG Channel 21 Control wb_trig_iface_ch21_ctl CH21_CTL
0x40 REG Channel 21 Configuration Parameters wb_trig_iface_ch21_cfg CH21_CFG
0x41 REG Channel 21 Transmitter/Receiver Pulses Counter wb_trig_iface_ch21_count CH21_COUNT
0x42 REG Channel 22 Control wb_trig_iface_ch22_ctl CH22_CTL
0x43 REG Channel 22 Configuration Parameters wb_trig_iface_ch22_cfg CH22_CFG
0x44 REG Channel 22 Transmitter/Receiver Pulses Counter wb_trig_iface_ch22_count CH22_COUNT
0x45 REG Channel 23 Control wb_trig_iface_ch23_ctl CH23_CTL
0x46 REG Channel 23 Configuration Parameters wb_trig_iface_ch23_cfg CH23_CFG
0x47 REG Channel 23 Transmitter/Receiver Pulses Counter wb_trig_iface_ch23_count CH23_COUNT

2. HDL symbol

rst_n_i Channel 0 Control:
clk_sys_i wb_trig_iface_ch0_ctl_dir_o
wb_adr_i[6:0] wb_trig_iface_ch0_ctl_dir_pol_o
wb_dat_i[31:0] wb_trig_iface_ch0_ctl_rcv_count_rst_o
wb_dat_o[31:0] wb_trig_iface_ch0_ctl_transm_count_rst_o
wb_cyc_i  
wb_sel_i[3:0] Channel 0 Configuration Parameters:
wb_stb_i wb_trig_iface_ch0_cfg_rcv_len_o[7:0]
wb_we_i wb_trig_iface_ch0_cfg_transm_len_o[7:0]
wb_ack_o  
wb_stall_o Channel 0 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch0_count_rcv_i[15:0]
wb_trig_iface_ch0_count_transm_i[15:0]
 
Channel 1 Control:
wb_trig_iface_ch1_ctl_dir_o
wb_trig_iface_ch1_ctl_dir_pol_o
wb_trig_iface_ch1_ctl_rcv_count_rst_o
wb_trig_iface_ch1_ctl_transm_count_rst_o
 
Channel 1 Configuration Parameters:
wb_trig_iface_ch1_cfg_rcv_len_o[7:0]
wb_trig_iface_ch1_cfg_transm_len_o[7:0]
 
Channel 1 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch1_count_rcv_i[15:0]
wb_trig_iface_ch1_count_transm_i[15:0]
 
Channel 2 Control:
wb_trig_iface_ch2_ctl_dir_o
wb_trig_iface_ch2_ctl_dir_pol_o
wb_trig_iface_ch2_ctl_rcv_count_rst_o
wb_trig_iface_ch2_ctl_transm_count_rst_o
 
Channel 2 Configuration Parameters:
wb_trig_iface_ch2_cfg_rcv_len_o[7:0]
wb_trig_iface_ch2_cfg_transm_len_o[7:0]
 
Channel 2 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch2_count_rcv_i[15:0]
wb_trig_iface_ch2_count_transm_i[15:0]
 
Channel 3 Control:
wb_trig_iface_ch3_ctl_dir_o
wb_trig_iface_ch3_ctl_dir_pol_o
wb_trig_iface_ch3_ctl_rcv_count_rst_o
wb_trig_iface_ch3_ctl_transm_count_rst_o
 
Channel 3 Configuration Parameters:
wb_trig_iface_ch3_cfg_rcv_len_o[7:0]
wb_trig_iface_ch3_cfg_transm_len_o[7:0]
 
Channel 3 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch3_count_rcv_i[15:0]
wb_trig_iface_ch3_count_transm_i[15:0]
 
Channel 4 Control:
wb_trig_iface_ch4_ctl_dir_o
wb_trig_iface_ch4_ctl_dir_pol_o
wb_trig_iface_ch4_ctl_rcv_count_rst_o
wb_trig_iface_ch4_ctl_transm_count_rst_o
 
Channel 4 Configuration Parameters:
wb_trig_iface_ch4_cfg_rcv_len_o[7:0]
wb_trig_iface_ch4_cfg_transm_len_o[7:0]
 
Channel 4 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch4_count_rcv_i[15:0]
wb_trig_iface_ch4_count_transm_i[15:0]
 
Channel 5 Control:
wb_trig_iface_ch5_ctl_dir_o
wb_trig_iface_ch5_ctl_dir_pol_o
wb_trig_iface_ch5_ctl_rcv_count_rst_o
wb_trig_iface_ch5_ctl_transm_count_rst_o
 
Channel 5 Configuration Parameters:
wb_trig_iface_ch5_cfg_rcv_len_o[7:0]
wb_trig_iface_ch5_cfg_transm_len_o[7:0]
 
Channel 5 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch5_count_rcv_i[15:0]
wb_trig_iface_ch5_count_transm_i[15:0]
 
Channel 6 Control:
wb_trig_iface_ch6_ctl_dir_o
wb_trig_iface_ch6_ctl_dir_pol_o
wb_trig_iface_ch6_ctl_rcv_count_rst_o
wb_trig_iface_ch6_ctl_transm_count_rst_o
 
Channel 6 Configuration Parameters:
wb_trig_iface_ch6_cfg_rcv_len_o[7:0]
wb_trig_iface_ch6_cfg_transm_len_o[7:0]
 
Channel 6 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch6_count_rcv_i[15:0]
wb_trig_iface_ch6_count_transm_i[15:0]
 
Channel 7 Control:
wb_trig_iface_ch7_ctl_dir_o
wb_trig_iface_ch7_ctl_dir_pol_o
wb_trig_iface_ch7_ctl_rcv_count_rst_o
wb_trig_iface_ch7_ctl_transm_count_rst_o
 
Channel 7 Configuration Parameters:
wb_trig_iface_ch7_cfg_rcv_len_o[7:0]
wb_trig_iface_ch7_cfg_transm_len_o[7:0]
 
Channel 7 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch7_count_rcv_i[15:0]
wb_trig_iface_ch7_count_transm_i[15:0]
 
Channel 8 Control:
wb_trig_iface_ch8_ctl_dir_o
wb_trig_iface_ch8_ctl_dir_pol_o
wb_trig_iface_ch8_ctl_rcv_count_rst_o
wb_trig_iface_ch8_ctl_transm_count_rst_o
 
Channel 8 Configuration Parameters:
wb_trig_iface_ch8_cfg_rcv_len_o[7:0]
wb_trig_iface_ch8_cfg_transm_len_o[7:0]
 
Channel 8 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch8_count_rcv_i[15:0]
wb_trig_iface_ch8_count_transm_i[15:0]
 
Channel 9 Control:
wb_trig_iface_ch9_ctl_dir_o
wb_trig_iface_ch9_ctl_dir_pol_o
wb_trig_iface_ch9_ctl_rcv_count_rst_o
wb_trig_iface_ch9_ctl_transm_count_rst_o
 
Channel 9 Configuration Parameters:
wb_trig_iface_ch9_cfg_rcv_len_o[7:0]
wb_trig_iface_ch9_cfg_transm_len_o[7:0]
 
Channel 9 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch9_count_rcv_i[15:0]
wb_trig_iface_ch9_count_transm_i[15:0]
 
Channel 10 Control:
wb_trig_iface_ch10_ctl_dir_o
wb_trig_iface_ch10_ctl_dir_pol_o
wb_trig_iface_ch10_ctl_rcv_count_rst_o
wb_trig_iface_ch10_ctl_transm_count_rst_o
 
Channel 10 Configuration Parameters:
wb_trig_iface_ch10_cfg_rcv_len_o[7:0]
wb_trig_iface_ch10_cfg_transm_len_o[7:0]
 
Channel 10 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch10_count_rcv_i[15:0]
wb_trig_iface_ch10_count_transm_i[15:0]
 
Channel 11 Control:
wb_trig_iface_ch11_ctl_dir_o
wb_trig_iface_ch11_ctl_dir_pol_o
wb_trig_iface_ch11_ctl_rcv_count_rst_o
wb_trig_iface_ch11_ctl_transm_count_rst_o
 
Channel 11 Configuration Parameters:
wb_trig_iface_ch11_cfg_rcv_len_o[7:0]
wb_trig_iface_ch11_cfg_transm_len_o[7:0]
 
Channel 11 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch11_count_rcv_i[15:0]
wb_trig_iface_ch11_count_transm_i[15:0]
 
Channel 12 Control:
wb_trig_iface_ch12_ctl_dir_o
wb_trig_iface_ch12_ctl_dir_pol_o
wb_trig_iface_ch12_ctl_rcv_count_rst_o
wb_trig_iface_ch12_ctl_transm_count_rst_o
 
Channel 12 Configuration Parameters:
wb_trig_iface_ch12_cfg_rcv_len_o[7:0]
wb_trig_iface_ch12_cfg_transm_len_o[7:0]
 
Channel 12 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch12_count_rcv_i[15:0]
wb_trig_iface_ch12_count_transm_i[15:0]
 
Channel 13 Control:
wb_trig_iface_ch13_ctl_dir_o
wb_trig_iface_ch13_ctl_dir_pol_o
wb_trig_iface_ch13_ctl_rcv_count_rst_o
wb_trig_iface_ch13_ctl_transm_count_rst_o
 
Channel 13 Configuration Parameters:
wb_trig_iface_ch13_cfg_rcv_len_o[7:0]
wb_trig_iface_ch13_cfg_transm_len_o[7:0]
 
Channel 13 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch13_count_rcv_i[15:0]
wb_trig_iface_ch13_count_transm_i[15:0]
 
Channel 14 Control:
wb_trig_iface_ch14_ctl_dir_o
wb_trig_iface_ch14_ctl_dir_pol_o
wb_trig_iface_ch14_ctl_rcv_count_rst_o
wb_trig_iface_ch14_ctl_transm_count_rst_o
 
Channel 14 Configuration Parameters:
wb_trig_iface_ch14_cfg_rcv_len_o[7:0]
wb_trig_iface_ch14_cfg_transm_len_o[7:0]
 
Channel 14 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch14_count_rcv_i[15:0]
wb_trig_iface_ch14_count_transm_i[15:0]
 
Channel 15 Control:
wb_trig_iface_ch15_ctl_dir_o
wb_trig_iface_ch15_ctl_dir_pol_o
wb_trig_iface_ch15_ctl_rcv_count_rst_o
wb_trig_iface_ch15_ctl_transm_count_rst_o
 
Channel 15 Configuration Parameters:
wb_trig_iface_ch15_cfg_rcv_len_o[7:0]
wb_trig_iface_ch15_cfg_transm_len_o[7:0]
 
Channel 15 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch15_count_rcv_i[15:0]
wb_trig_iface_ch15_count_transm_i[15:0]
 
Channel 16 Control:
wb_trig_iface_ch16_ctl_dir_o
wb_trig_iface_ch16_ctl_dir_pol_o
wb_trig_iface_ch16_ctl_rcv_count_rst_o
wb_trig_iface_ch16_ctl_transm_count_rst_o
 
Channel 16 Configuration Parameters:
wb_trig_iface_ch16_cfg_rcv_len_o[7:0]
wb_trig_iface_ch16_cfg_transm_len_o[7:0]
 
Channel 16 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch16_count_rcv_i[15:0]
wb_trig_iface_ch16_count_transm_i[15:0]
 
Channel 17 Control:
wb_trig_iface_ch17_ctl_dir_o
wb_trig_iface_ch17_ctl_dir_pol_o
wb_trig_iface_ch17_ctl_rcv_count_rst_o
wb_trig_iface_ch17_ctl_transm_count_rst_o
 
Channel 17 Configuration Parameters:
wb_trig_iface_ch17_cfg_rcv_len_o[7:0]
wb_trig_iface_ch17_cfg_transm_len_o[7:0]
 
Channel 17 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch17_count_rcv_i[15:0]
wb_trig_iface_ch17_count_transm_i[15:0]
 
Channel 18 Control:
wb_trig_iface_ch18_ctl_dir_o
wb_trig_iface_ch18_ctl_dir_pol_o
wb_trig_iface_ch18_ctl_rcv_count_rst_o
wb_trig_iface_ch18_ctl_transm_count_rst_o
 
Channel 18 Configuration Parameters:
wb_trig_iface_ch18_cfg_rcv_len_o[7:0]
wb_trig_iface_ch18_cfg_transm_len_o[7:0]
 
Channel 18 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch18_count_rcv_i[15:0]
wb_trig_iface_ch18_count_transm_i[15:0]
 
Channel 19 Control:
wb_trig_iface_ch19_ctl_dir_o
wb_trig_iface_ch19_ctl_dir_pol_o
wb_trig_iface_ch19_ctl_rcv_count_rst_o
wb_trig_iface_ch19_ctl_transm_count_rst_o
 
Channel 19 Configuration Parameters:
wb_trig_iface_ch19_cfg_rcv_len_o[7:0]
wb_trig_iface_ch19_cfg_transm_len_o[7:0]
 
Channel 19 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch19_count_rcv_i[15:0]
wb_trig_iface_ch19_count_transm_i[15:0]
 
Channel 20 Control:
wb_trig_iface_ch20_ctl_dir_o
wb_trig_iface_ch20_ctl_dir_pol_o
wb_trig_iface_ch20_ctl_rcv_count_rst_o
wb_trig_iface_ch20_ctl_transm_count_rst_o
 
Channel 20 Configuration Parameters:
wb_trig_iface_ch20_cfg_rcv_len_o[7:0]
wb_trig_iface_ch20_cfg_transm_len_o[7:0]
 
Channel 20 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch20_count_rcv_i[15:0]
wb_trig_iface_ch20_count_transm_i[15:0]
 
Channel 21 Control:
wb_trig_iface_ch21_ctl_dir_o
wb_trig_iface_ch21_ctl_dir_pol_o
wb_trig_iface_ch21_ctl_rcv_count_rst_o
wb_trig_iface_ch21_ctl_transm_count_rst_o
 
Channel 21 Configuration Parameters:
wb_trig_iface_ch21_cfg_rcv_len_o[7:0]
wb_trig_iface_ch21_cfg_transm_len_o[7:0]
 
Channel 21 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch21_count_rcv_i[15:0]
wb_trig_iface_ch21_count_transm_i[15:0]
 
Channel 22 Control:
wb_trig_iface_ch22_ctl_dir_o
wb_trig_iface_ch22_ctl_dir_pol_o
wb_trig_iface_ch22_ctl_rcv_count_rst_o
wb_trig_iface_ch22_ctl_transm_count_rst_o
 
Channel 22 Configuration Parameters:
wb_trig_iface_ch22_cfg_rcv_len_o[7:0]
wb_trig_iface_ch22_cfg_transm_len_o[7:0]
 
Channel 22 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch22_count_rcv_i[15:0]
wb_trig_iface_ch22_count_transm_i[15:0]
 
Channel 23 Control:
wb_trig_iface_ch23_ctl_dir_o
wb_trig_iface_ch23_ctl_dir_pol_o
wb_trig_iface_ch23_ctl_rcv_count_rst_o
wb_trig_iface_ch23_ctl_transm_count_rst_o
 
Channel 23 Configuration Parameters:
wb_trig_iface_ch23_cfg_rcv_len_o[7:0]
wb_trig_iface_ch23_cfg_transm_len_o[7:0]
 
Channel 23 Transmitter/Receiver Pulses Counter:
wb_trig_iface_ch23_count_rcv_i[15:0]
wb_trig_iface_ch23_count_transm_i[15:0]

3. Register description

3.1. Channel 0 Control

HW prefix: wb_trig_iface_ch0_ctl
HW address: 0x0
C prefix: CH0_CTL
C offset: 0x0
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.2. Channel 0 Configuration Parameters

HW prefix: wb_trig_iface_ch0_cfg
HW address: 0x1
C prefix: CH0_CFG
C offset: 0x4
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.3. Channel 0 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch0_count
HW address: 0x2
C prefix: CH0_COUNT
C offset: 0x8
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.4. Channel 1 Control

HW prefix: wb_trig_iface_ch1_ctl
HW address: 0x3
C prefix: CH1_CTL
C offset: 0xc
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.5. Channel 1 Configuration Parameters

HW prefix: wb_trig_iface_ch1_cfg
HW address: 0x4
C prefix: CH1_CFG
C offset: 0x10
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.6. Channel 1 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch1_count
HW address: 0x5
C prefix: CH1_COUNT
C offset: 0x14
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.7. Channel 2 Control

HW prefix: wb_trig_iface_ch2_ctl
HW address: 0x6
C prefix: CH2_CTL
C offset: 0x18
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.8. Channel 2 Configuration Parameters

HW prefix: wb_trig_iface_ch2_cfg
HW address: 0x7
C prefix: CH2_CFG
C offset: 0x1c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.9. Channel 2 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch2_count
HW address: 0x8
C prefix: CH2_COUNT
C offset: 0x20
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.10. Channel 3 Control

HW prefix: wb_trig_iface_ch3_ctl
HW address: 0x9
C prefix: CH3_CTL
C offset: 0x24
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.11. Channel 3 Configuration Parameters

HW prefix: wb_trig_iface_ch3_cfg
HW address: 0xa
C prefix: CH3_CFG
C offset: 0x28
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.12. Channel 3 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch3_count
HW address: 0xb
C prefix: CH3_COUNT
C offset: 0x2c
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.13. Channel 4 Control

HW prefix: wb_trig_iface_ch4_ctl
HW address: 0xc
C prefix: CH4_CTL
C offset: 0x30
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.14. Channel 4 Configuration Parameters

HW prefix: wb_trig_iface_ch4_cfg
HW address: 0xd
C prefix: CH4_CFG
C offset: 0x34
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.15. Channel 4 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch4_count
HW address: 0xe
C prefix: CH4_COUNT
C offset: 0x38
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.16. Channel 5 Control

HW prefix: wb_trig_iface_ch5_ctl
HW address: 0xf
C prefix: CH5_CTL
C offset: 0x3c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.17. Channel 5 Configuration Parameters

HW prefix: wb_trig_iface_ch5_cfg
HW address: 0x10
C prefix: CH5_CFG
C offset: 0x40
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.18. Channel 5 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch5_count
HW address: 0x11
C prefix: CH5_COUNT
C offset: 0x44
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.19. Channel 6 Control

HW prefix: wb_trig_iface_ch6_ctl
HW address: 0x12
C prefix: CH6_CTL
C offset: 0x48
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.20. Channel 6 Configuration Parameters

HW prefix: wb_trig_iface_ch6_cfg
HW address: 0x13
C prefix: CH6_CFG
C offset: 0x4c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.21. Channel 6 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch6_count
HW address: 0x14
C prefix: CH6_COUNT
C offset: 0x50
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.22. Channel 7 Control

HW prefix: wb_trig_iface_ch7_ctl
HW address: 0x15
C prefix: CH7_CTL
C offset: 0x54
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.23. Channel 7 Configuration Parameters

HW prefix: wb_trig_iface_ch7_cfg
HW address: 0x16
C prefix: CH7_CFG
C offset: 0x58
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.24. Channel 7 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch7_count
HW address: 0x17
C prefix: CH7_COUNT
C offset: 0x5c
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.25. Channel 8 Control

HW prefix: wb_trig_iface_ch8_ctl
HW address: 0x18
C prefix: CH8_CTL
C offset: 0x60
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.26. Channel 8 Configuration Parameters

HW prefix: wb_trig_iface_ch8_cfg
HW address: 0x19
C prefix: CH8_CFG
C offset: 0x64
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.27. Channel 8 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch8_count
HW address: 0x1a
C prefix: CH8_COUNT
C offset: 0x68
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.28. Channel 9 Control

HW prefix: wb_trig_iface_ch9_ctl
HW address: 0x1b
C prefix: CH9_CTL
C offset: 0x6c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.29. Channel 9 Configuration Parameters

HW prefix: wb_trig_iface_ch9_cfg
HW address: 0x1c
C prefix: CH9_CFG
C offset: 0x70
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.30. Channel 9 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch9_count
HW address: 0x1d
C prefix: CH9_COUNT
C offset: 0x74
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.31. Channel 10 Control

HW prefix: wb_trig_iface_ch10_ctl
HW address: 0x1e
C prefix: CH10_CTL
C offset: 0x78
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.32. Channel 10 Configuration Parameters

HW prefix: wb_trig_iface_ch10_cfg
HW address: 0x1f
C prefix: CH10_CFG
C offset: 0x7c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.33. Channel 10 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch10_count
HW address: 0x20
C prefix: CH10_COUNT
C offset: 0x80
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.34. Channel 11 Control

HW prefix: wb_trig_iface_ch11_ctl
HW address: 0x21
C prefix: CH11_CTL
C offset: 0x84
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.35. Channel 11 Configuration Parameters

HW prefix: wb_trig_iface_ch11_cfg
HW address: 0x22
C prefix: CH11_CFG
C offset: 0x88
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.36. Channel 11 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch11_count
HW address: 0x23
C prefix: CH11_COUNT
C offset: 0x8c
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.37. Channel 12 Control

HW prefix: wb_trig_iface_ch12_ctl
HW address: 0x24
C prefix: CH12_CTL
C offset: 0x90
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.38. Channel 12 Configuration Parameters

HW prefix: wb_trig_iface_ch12_cfg
HW address: 0x25
C prefix: CH12_CFG
C offset: 0x94
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.39. Channel 12 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch12_count
HW address: 0x26
C prefix: CH12_COUNT
C offset: 0x98
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.40. Channel 13 Control

HW prefix: wb_trig_iface_ch13_ctl
HW address: 0x27
C prefix: CH13_CTL
C offset: 0x9c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.41. Channel 13 Configuration Parameters

HW prefix: wb_trig_iface_ch13_cfg
HW address: 0x28
C prefix: CH13_CFG
C offset: 0xa0
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.42. Channel 13 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch13_count
HW address: 0x29
C prefix: CH13_COUNT
C offset: 0xa4
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.43. Channel 14 Control

HW prefix: wb_trig_iface_ch14_ctl
HW address: 0x2a
C prefix: CH14_CTL
C offset: 0xa8
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.44. Channel 14 Configuration Parameters

HW prefix: wb_trig_iface_ch14_cfg
HW address: 0x2b
C prefix: CH14_CFG
C offset: 0xac
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.45. Channel 14 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch14_count
HW address: 0x2c
C prefix: CH14_COUNT
C offset: 0xb0
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.46. Channel 15 Control

HW prefix: wb_trig_iface_ch15_ctl
HW address: 0x2d
C prefix: CH15_CTL
C offset: 0xb4
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.47. Channel 15 Configuration Parameters

HW prefix: wb_trig_iface_ch15_cfg
HW address: 0x2e
C prefix: CH15_CFG
C offset: 0xb8
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.48. Channel 15 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch15_count
HW address: 0x2f
C prefix: CH15_COUNT
C offset: 0xbc
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.49. Channel 16 Control

HW prefix: wb_trig_iface_ch16_ctl
HW address: 0x30
C prefix: CH16_CTL
C offset: 0xc0
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.50. Channel 16 Configuration Parameters

HW prefix: wb_trig_iface_ch16_cfg
HW address: 0x31
C prefix: CH16_CFG
C offset: 0xc4
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.51. Channel 16 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch16_count
HW address: 0x32
C prefix: CH16_COUNT
C offset: 0xc8
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.52. Channel 17 Control

HW prefix: wb_trig_iface_ch17_ctl
HW address: 0x33
C prefix: CH17_CTL
C offset: 0xcc
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.53. Channel 17 Configuration Parameters

HW prefix: wb_trig_iface_ch17_cfg
HW address: 0x34
C prefix: CH17_CFG
C offset: 0xd0
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.54. Channel 17 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch17_count
HW address: 0x35
C prefix: CH17_COUNT
C offset: 0xd4
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.55. Channel 18 Control

HW prefix: wb_trig_iface_ch18_ctl
HW address: 0x36
C prefix: CH18_CTL
C offset: 0xd8
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.56. Channel 18 Configuration Parameters

HW prefix: wb_trig_iface_ch18_cfg
HW address: 0x37
C prefix: CH18_CFG
C offset: 0xdc
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.57. Channel 18 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch18_count
HW address: 0x38
C prefix: CH18_COUNT
C offset: 0xe0
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.58. Channel 19 Control

HW prefix: wb_trig_iface_ch19_ctl
HW address: 0x39
C prefix: CH19_CTL
C offset: 0xe4
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.59. Channel 19 Configuration Parameters

HW prefix: wb_trig_iface_ch19_cfg
HW address: 0x3a
C prefix: CH19_CFG
C offset: 0xe8
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.60. Channel 19 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch19_count
HW address: 0x3b
C prefix: CH19_COUNT
C offset: 0xec
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.61. Channel 20 Control

HW prefix: wb_trig_iface_ch20_ctl
HW address: 0x3c
C prefix: CH20_CTL
C offset: 0xf0
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.62. Channel 20 Configuration Parameters

HW prefix: wb_trig_iface_ch20_cfg
HW address: 0x3d
C prefix: CH20_CFG
C offset: 0xf4
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.63. Channel 20 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch20_count
HW address: 0x3e
C prefix: CH20_COUNT
C offset: 0xf8
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.64. Channel 21 Control

HW prefix: wb_trig_iface_ch21_ctl
HW address: 0x3f
C prefix: CH21_CTL
C offset: 0xfc
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.65. Channel 21 Configuration Parameters

HW prefix: wb_trig_iface_ch21_cfg
HW address: 0x40
C prefix: CH21_CFG
C offset: 0x100
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.66. Channel 21 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch21_count
HW address: 0x41
C prefix: CH21_COUNT
C offset: 0x104
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.67. Channel 22 Control

HW prefix: wb_trig_iface_ch22_ctl
HW address: 0x42
C prefix: CH22_CTL
C offset: 0x108
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.68. Channel 22 Configuration Parameters

HW prefix: wb_trig_iface_ch22_cfg
HW address: 0x43
C prefix: CH22_CFG
C offset: 0x10c
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.69. Channel 22 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch22_count
HW address: 0x44
C prefix: CH22_COUNT
C offset: 0x110
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]

3.70. Channel 23 Control

HW prefix: wb_trig_iface_ch23_ctl
HW address: 0x45
C prefix: CH23_CTL
C offset: 0x114
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - TRANSM_COUNT_RST RCV_COUNT_RST DIR_POL DIR

3.71. Channel 23 Configuration Parameters

HW prefix: wb_trig_iface_ch23_cfg
HW address: 0x46
C prefix: CH23_CFG
C offset: 0x118
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
TRANSM_LEN[7:0]
7 6 5 4 3 2 1 0
RCV_LEN[7:0]

3.72. Channel 23 Transmitter/Receiver Pulses Counter

HW prefix: wb_trig_iface_ch23_count
HW address: 0x47
C prefix: CH23_COUNT
C offset: 0x11c
31 30 29 28 27 26 25 24
TRANSM[15:8]
23 22 21 20 19 18 17 16
TRANSM[7:0]
15 14 13 12 11 10 9 8
RCV[15:8]
7 6 5 4 3 2 1 0
RCV[7:0]