wb_dma_ctl_iface
Wishbone DMA Streaming Control Interface
Simple Wishbone DMA interface for controlling the DMA Streaming peripheral
Contents:
1. Memory map summary
2. HDL symbol
3. Register description
3.1. Control/Status register
3.2. Transaction Counter
→
|
rst_n_i
|
|
Control/Status register:
|
|
→
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clk_sys_i
|
|
dma_ctl_iface_ctl_start_o
|
→
|
→
|
wb_adr_i
|
|
dma_ctl_iface_ctl_done_i
|
←
|
⇒
|
wb_dat_i[31:0]
|
|
dma_ctl_iface_ctl_ovf_i
|
←
|
⇐
|
wb_dat_o[31:0]
|
|
|
|
→
|
wb_cyc_i
|
|
Transaction Counter:
|
|
⇒
|
wb_sel_i[3:0]
|
|
dma_ctl_iface_tr_cntr_o[31:0]
|
⇒
|
→
|
wb_stb_i
|
|
|
|
→
|
wb_we_i
|
|
|
|
←
|
wb_ack_o
|
|
|
|
←
|
wb_stall_o
|
|
|
|
HW prefix:
|
dma_ctl_iface_ctl
|
HW address:
|
0x0
|
C prefix:
|
CTL
|
C offset:
|
0x0
|
A register defining the Control and Status of the core.
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
-
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
-
|
-
|
-
|
-
|
-
|
OVF
|
DONE
|
START
|
-
START
[read/write]: Start Transaction
write 1: starts the DMA transaction.
write 0: no effect
-
DONE
[read-only]: DMA complete
read 1: the DMA has completed the transaction
read 0: DMA transaction still in progress
-
OVF
[read-only]: DMA overflow
read 1: the DMA overflow detected
read 0: No overflow detected
HW prefix:
|
dma_ctl_iface_tr_cntr
|
HW address:
|
0x1
|
C prefix:
|
TR_CNTR
|
C offset:
|
0x4
|
Register holding the word count to be transfered to DMA
31
|
30
|
29
|
28
|
27
|
26
|
25
|
24
|
TR_CNTR[31:24]
|
|
|
|
|
|
|
|
23
|
22
|
21
|
20
|
19
|
18
|
17
|
16
|
TR_CNTR[23:16]
|
|
|
|
|
|
|
|
15
|
14
|
13
|
12
|
11
|
10
|
9
|
8
|
TR_CNTR[15:8]
|
|
|
|
|
|
|
|
7
|
6
|
5
|
4
|
3
|
2
|
1
|
0
|
TR_CNTR[7:0]
|
|
|
|
|
|
|
|
-
TR_CNTR
[read/write]: Transactions Counter
Stores the words to be transfered to DMA