FMC TDC 1ns 5cha
The FMC TDC 1ns 5cha Time to Digital Converter mezzanine board houses 5
input channels. It can calculate time differences between pulses
arriving to the channels with a precision of ±700 ps.
It can be carried by any of the carrier boards:
SPEC or
SVEC. It is implemented using
a dedicated time-to-digital converter chip from the European company
ACAM.
SVEC carrier with two slots for TDC mezzanines and SPEC carrier with one slot for a TDC mezzanine (more TDC views )
Links
- v8 Performance
- v7 Hardware, Gateware and Software long runs on SVEC
- v7 TDC Precision
- v7 TDC Performance
- How to set up the spec and fmc tdc with epics
Contact
Licences
- Creative Commons Attribution Share Alike 4.0 International
- CERN Open Hardware Licence Version 2 - Weakly Reciprocal
- GNU Lesser General Public License v2.1 only
- GNU Lesser General Public License v2.1 or later
Tags
Documentation Software GatewareCompatible Projects
FMC TDC 1ns 5cha - Hardware
The Time to Digital Converter board, FMC TDC 1ns 5cha (EDA-02290) is an FMC mezzanine board with five input channels
Latest News
02-02-2012: V2 design ready
Based on the experience with the V1 prototype, nine Issues were found. Corrections have been made to the schematics and PCB layout and these will be reviewed on 7 February. After this CERN’s design office will generate the final production files. The firmware VHDL code is under thorough review and production test software has to be written. This work should be ready by the end of the summer.
30-05-2011: 3 prototypes assembled
Three prototypes of the Time to Digital converter have been built. We made a start of the VHDL coding for use on the SPEC PCI Express FMC carrier.
18-03-2011: Schematics design review held
After a first global schematics review in the week before, a second schematics design review was held with five engineers who found a few details that will improve the functioning and the documentation of the schematics. The PCB layout will likely start in a week’s time.