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-- Title          : Wishbone slave core for Clock Frequency Monitor
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-- File           : clock_monitor_wbgen2_pkg.vhd
-- Author         : auto-generated by wbgen2 from clock_monitor_wb.wb
-- Created        : Mon Jun 17 18:28:42 2019
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE clock_monitor_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

package cm_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_cm_in_registers is record
    cnt_val_value_i                          : std_logic_vector(30 downto 0);
    cnt_val_valid_i                          : std_logic;
  end record;
  
  constant c_cm_in_registers_init_value: t_cm_in_registers := (
    cnt_val_value_i => (others => '0'),
    cnt_val_valid_i => '0'
  );
  
  -- Output registers (WB slave -> user design)
  
  type t_cm_out_registers is record
    cr_cnt_rst_o                             : std_logic;
    cr_presc_o                               : std_logic_vector(7 downto 0);
    cr_refsel_o                              : std_logic_vector(3 downto 0);
    refdr_refdr_o                            : std_logic_vector(31 downto 0);
    cnt_sel_sel_o                            : std_logic_vector(3 downto 0);
    cnt_val_valid_o                          : std_logic;
    cnt_val_valid_load_o                     : std_logic;
  end record;
  
  constant c_cm_out_registers_init_value: t_cm_out_registers := (
    cr_cnt_rst_o => '0',
    cr_presc_o => (others => '0'),
    cr_refsel_o => (others => '0'),
    refdr_refdr_o => (others => '0'),
    cnt_sel_sel_o => (others => '0'),
    cnt_val_valid_o => '0',
    cnt_val_valid_load_o => '0'
  );

function "or" (left, right: t_cm_in_registers) return t_cm_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;

component clock_monitor_wb is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    slave_i                                  : in     t_wishbone_slave_in;
    slave_o                                  : out    t_wishbone_slave_out;
    int_o                                    : out    std_logic;
    regs_i                                   : in     t_cm_in_registers;
    regs_o                                   : out    t_cm_out_registers
  );
end component;

end package;

package body cm_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
  if x = '1' then
    return '1';
  else
    return '0';
  end if;
end function;

function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
  variable tmp: std_logic_vector(x'length-1 downto 0);
begin
  for i in 0 to x'length-1 loop
    if(x(i) = 'X' or x(i) = 'U') then
      tmp(i):= '0';
    else
      tmp(i):=x(i);
    end if; 
  end loop; 
  return tmp;
end function;

function "or" (left, right: t_cm_in_registers) return t_cm_in_registers is
  variable tmp: t_cm_in_registers;
begin
  tmp.cnt_val_value_i := f_x_to_zero(left.cnt_val_value_i) or f_x_to_zero(right.cnt_val_value_i);
  tmp.cnt_val_valid_i := f_x_to_zero(left.cnt_val_valid_i) or f_x_to_zero(right.cnt_val_valid_i);
  return tmp;
end function;

end package body;
