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-- Title          : Wishbone slave core for Clock Frequency Monitor
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-- File           : clock_monitor_wb.vhd
-- Author         : auto-generated by wbgen2 from clock_monitor_wb.wb
-- Created        : Mon Jun 17 18:28:42 2019
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE clock_monitor_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

use work.cm_wbgen2_pkg.all;


entity clock_monitor_wb is
port (
  rst_n_i                                  : in     std_logic;
  clk_sys_i                                : in     std_logic;
  slave_i                                  : in     t_wishbone_slave_in;
  slave_o                                  : out    t_wishbone_slave_out;
  int_o                                    : out    std_logic;
  regs_i                                   : in     t_cm_in_registers;
  regs_o                                   : out    t_cm_out_registers
);
end clock_monitor_wb;

architecture syn of clock_monitor_wb is

signal cm_cr_cnt_rst_dly0                       : std_logic      ;
signal cm_cr_cnt_rst_int                        : std_logic      ;
signal cm_cr_presc_int                          : std_logic_vector(7 downto 0);
signal cm_cr_refsel_int                         : std_logic_vector(3 downto 0);
signal cm_refdr_refdr_int                       : std_logic_vector(31 downto 0);
signal cm_cnt_sel_sel_int                       : std_logic_vector(3 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(1 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
-- 
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
  if (rst_n_i = '0') then 
    ack_sreg <= "0000000000";
    ack_in_progress <= '0';
    rddata_reg <= "00000000000000000000000000000000";
    cm_cr_cnt_rst_int <= '0';
    cm_cr_presc_int <= "00000000";
    cm_cr_refsel_int <= "0000";
    cm_refdr_refdr_int <= "00000000000000000000000000000000";
    cm_cnt_sel_sel_int <= "0000";
    regs_o.cnt_val_valid_load_o <= '0';
  elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
    ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
    ack_sreg(9) <= '0';
    if (ack_in_progress = '1') then
      if (ack_sreg(0) = '1') then
        cm_cr_cnt_rst_int <= '0';
        regs_o.cnt_val_valid_load_o <= '0';
        ack_in_progress <= '0';
      else
        regs_o.cnt_val_valid_load_o <= '0';
      end if;
    else
      if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
        case rwaddr_reg(1 downto 0) is
        when "00" => 
          if (slave_i.we = '1') then
            cm_cr_cnt_rst_int <= wrdata_reg(0);
            cm_cr_presc_int <= wrdata_reg(8 downto 1);
            cm_cr_refsel_int <= wrdata_reg(12 downto 9);
          end if;
          rddata_reg(0) <= '0';
          rddata_reg(8 downto 1) <= cm_cr_presc_int;
          rddata_reg(12 downto 9) <= cm_cr_refsel_int;
          rddata_reg(13) <= 'X';
          rddata_reg(14) <= 'X';
          rddata_reg(15) <= 'X';
          rddata_reg(16) <= 'X';
          rddata_reg(17) <= 'X';
          rddata_reg(18) <= 'X';
          rddata_reg(19) <= 'X';
          rddata_reg(20) <= 'X';
          rddata_reg(21) <= 'X';
          rddata_reg(22) <= 'X';
          rddata_reg(23) <= 'X';
          rddata_reg(24) <= 'X';
          rddata_reg(25) <= 'X';
          rddata_reg(26) <= 'X';
          rddata_reg(27) <= 'X';
          rddata_reg(28) <= 'X';
          rddata_reg(29) <= 'X';
          rddata_reg(30) <= 'X';
          rddata_reg(31) <= 'X';
          ack_sreg(2) <= '1';
          ack_in_progress <= '1';
        when "01" => 
          if (slave_i.we = '1') then
            cm_refdr_refdr_int <= wrdata_reg(31 downto 0);
          end if;
          rddata_reg(31 downto 0) <= cm_refdr_refdr_int;
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "10" => 
          if (slave_i.we = '1') then
            cm_cnt_sel_sel_int <= wrdata_reg(3 downto 0);
          end if;
          rddata_reg(3 downto 0) <= cm_cnt_sel_sel_int;
          rddata_reg(4) <= 'X';
          rddata_reg(5) <= 'X';
          rddata_reg(6) <= 'X';
          rddata_reg(7) <= 'X';
          rddata_reg(8) <= 'X';
          rddata_reg(9) <= 'X';
          rddata_reg(10) <= 'X';
          rddata_reg(11) <= 'X';
          rddata_reg(12) <= 'X';
          rddata_reg(13) <= 'X';
          rddata_reg(14) <= 'X';
          rddata_reg(15) <= 'X';
          rddata_reg(16) <= 'X';
          rddata_reg(17) <= 'X';
          rddata_reg(18) <= 'X';
          rddata_reg(19) <= 'X';
          rddata_reg(20) <= 'X';
          rddata_reg(21) <= 'X';
          rddata_reg(22) <= 'X';
          rddata_reg(23) <= 'X';
          rddata_reg(24) <= 'X';
          rddata_reg(25) <= 'X';
          rddata_reg(26) <= 'X';
          rddata_reg(27) <= 'X';
          rddata_reg(28) <= 'X';
          rddata_reg(29) <= 'X';
          rddata_reg(30) <= 'X';
          rddata_reg(31) <= 'X';
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when "11" => 
          if (slave_i.we = '1') then
            regs_o.cnt_val_valid_load_o <= '1';
          end if;
          rddata_reg(30 downto 0) <= regs_i.cnt_val_value_i;
          rddata_reg(31) <= regs_i.cnt_val_valid_i;
          ack_sreg(0) <= '1';
          ack_in_progress <= '1';
        when others =>
-- prevent the slave from hanging the bus on invalid address
          ack_in_progress <= '1';
          ack_sreg(0) <= '1';
        end case;
      end if;
    end if;
  end if;
end process;


-- Drive the data output bus
slave_o.dat <= rddata_reg;
-- Reset counters
process (clk_sys_i, rst_n_i)
begin
  if (rst_n_i = '0') then 
    cm_cr_cnt_rst_dly0 <= '0';
    regs_o.cr_cnt_rst_o <= '0';
  elsif rising_edge(clk_sys_i) then
    cm_cr_cnt_rst_dly0 <= cm_cr_cnt_rst_int;
    regs_o.cr_cnt_rst_o <= cm_cr_cnt_rst_int and (not cm_cr_cnt_rst_dly0);
  end if;
end process;


-- Prescaler
regs_o.cr_presc_o <= cm_cr_presc_int;
-- Reference Select
regs_o.cr_refsel_o <= cm_cr_refsel_int;
-- Reference Division Ratio
regs_o.refdr_refdr_o <= cm_refdr_refdr_int;
-- Counter Select
regs_o.cnt_sel_sel_o <= cm_cnt_sel_sel_int;
-- Counter Value
-- Counter Value Valid/Clear
regs_o.cnt_val_valid_o <= wrdata_reg(31);
rwaddr_reg <= slave_i.adr(3 downto 2);
slave_o.stall <= (not ack_sreg(0)) and (slave_i.stb and slave_i.cyc);
slave_o.err <= '0';
slave_o.rty <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
slave_o.ack <= ack_sreg(0);
end syn;
