CASPER2016 / HPSPSA2016
added by Simon Winberg on 2015-08-25 09:20:31.181701
We're planning on having a RHINO tutorial during the 2016 Collaboration For Astronomy Signal Processing and Electronics Research (CASPER) workshop that is going to be held in Cape Town from 25-29 Jan 2016. The RHINO tutorial is planned for afternoon of the 27 Jan 2016. More info on the web at http://www.hpspsa.com/
Rhino tutorials at the HPSPSA Workshop 2014
added by Simon Winberg on 2014-02-02 07:51:39.425507
I’m happy to report that the Rhino platform tutorials went well at the HPSPSA workshop that took place at the end of January together with the ROACH tutorials that were offered by the SKA-SA team. A big thank you to Matthew Bridges, who is doing a MSc with the SDRG, for the tremendous effort he put in to making these tutorials a working reality. Due to the limited time available for the tutorial, we provided three parts: participants unfamiliar with Xilinx ISE could select to start at Tutorial 0; those already capable of VHDL coding could jump right to Tutorial 3 (we took out Tutorial 2 which relates to flashing the LEDs). Thanks to the participants who tried out our Rhino tutorials and for their feedback.
High-performance Signal and Data Processing Workshop 2014
added by Simon Winberg on 2013-11-08 15:38:29.843207
The next High-performance Signal and Data Processing in South Africa (HPSPSA) Workshop will take place between 27-31 January 2014 at the University of the Witwatersrand in Johannesburg, South Africa. The workshop aims to bring together key people to discuss grand challenges facing the signal processing community in Radio Astronomy, Gamma Ray Astronomy and Particle Physics, and to provide knowledge sharing to delegates in both a lecture format, as well as a classroom environment for hands-on hardware training. General overviews and in-depth presentations will be given. The conference focuses on signal processing for high performance applications based on FPGA-accelerator platforms, and will feature both local and international speakers. Tutorials on FPGA-based processing systems, including a tutorial on using the Rhino platform, will be available for participation.
Travel subsidies to attend or present a paper at the conference can be applied for. This year we're planning to bring our a peer-reviewed proceedings after the conference. To present and have a paper considered for inclusion in the proceedings, you need to submit an abstract of your presentation by 31 Dec 2013.
For more information please visit:
http://www.hpspsa.com/
Learn about Rhino in South Africa
added by Alan Langman on 2012-11-18 10:06:51.423966
The University of Cape Town, Stellenbosch University, and the Square Kilometer Array South Africa (SKA-SA) are organizing the 1st annual Workshop on High Performance Signal Processing (WHPSP) to be held at the University of Cape Town 28-31 January 2013. The workshop is three and a half days. Industry or acedemic partners that are not able to attend the whole conference are most welcome to join in the panel discussion held on 31 January at 9am. The conference focuses on signal processing for high performance applications based on FPGA-accelerator platforms, and will feature both local and international speakers. Tutorials on FPGA-based processing systems, including a tutorial on using the Rhino platform, will be available for participation.
This workshop is open to anyone with a background in signal processing. Limited financial support is available for students outside of Cape Town, and all students meeting selection criteria are encouraged to apply. If this email is misdirected, please could you forward it to all potentially interested parties, including relevant undergraduate and postgraduate students. See the website for more information: https://sites.google.com/site/hpdspworkshopcpt2012/.
Follow us on twitter
added by Alan Langman on 2011-08-18 17:51:12.481302
We now have 8 Rhino boards in the ether and a manufacturer in the US
willing to provide you with you very own platform for a few $$$. We
thought it would be a good time to more actively update the community on
progress and the efforts of the various pioneers through social media.
All welcome to follow and comment.
- the rhino team
Some Updates
added by Alan Langman on 2011-08-17 23:15:11.099312
It has been a while since I last added a news item. The Rhino project has still been moving along at a steady albeit slow (part time) effort. The first version of Rhino had a few minor bugs which we fixed in version 1.1. We managed to find some money to build a few more boards; 6 to be exact; with 5 working and one needing a bit of rework. Lots of effort has been spent on the software tools, which currently reside on github (linked off www.borph.org). Rhino V1.1 sports a cutting edge Borph enabled Linux 3.1 RC 1 kernel, thanks to some late night efforts from Brandon. Next step is lots of gateware.
Borph/Linux
added by Alan Langman on 2011-03-29 23:51:45.568745
We have finally finish setting to work the full Rhino board with a port of Borph Linux. BORPH is an operating system designed for FPGA-based reconfigurable computers, implemented as an extension of the Linux kernel. Reconfigurable hardware, such as FPGAs, are treated as computational resources within the operating system (www.borph.org)
Great Progress!
added by Alan Langman on 2011-01-28 10:37:57.396723
Simon and Bruce have been busy setting to work the Rhino platform and making excellent progress. Last night we had the first successful communications between the two CX4 ports at full throttle. After 10 million 64-bit frames (simultaneous data transmission between CX4 ports), we had zero errors with a 0.5m cable. The eye diagrams look good out to 2m cables, so for long cables we will need to go optical.
The SPI interface is now working through uboot and has been used to probe the RTC and configure the FPGA.
Just three more interfaces to test! GPMC, 1Ge and FMC.
Rhino is alive!
added by Alan Langman on 2010-12-31 16:52:12.693848
It was tight, but we made it; our first 4 prototypes have arrived and Simon is busy setting them to work. Thanks to everyone that helped! Current testing focus is on the processor subsystem. We currently have a u-boot prompt; booting from the SD Card. Progress is good and we looking forward to completing all our testing in January.
Happy New Year to All!
Rhino layout complete and ready for review!
added by Alan Langman on 2010-11-11 13:24:28.739015
It has been a challenge, but we finally managed to complete the Rhino
layout; thanks to a great effort by the team. The board ended up with 14
layers, a few more than we originally anticipated, but that is to be
expected when most of the routes were targeted impedance, length matched
and differential. All the latest Altium design files have been
uploaded
to the Rhino svn repository (http://svn.ohwr.org/rhino-hardware-01). If
you have the time please review and send to us feedback by the end of
Monday, November 15th.
PCB layout almost complete
added by Alan Langman on 2010-10-26 21:45:45.320695
Layout has taken a bit longer than anticipated, however the end is now in sight! Supporting dual FMC-LPC connectors, DDR3 memory and various other high speed signals, placed some stringent impedance and length matching rules on many of the nets from the FPGA. As a result, the layout process was somewhat challenging. We ended up with 14 layers to accomodate all the constrained signal-ended and differential nets. For those interested we have placed an image of the Altium 3D CAD model for Rhino on the project wiki page.
RHINO Project Page update
added by Alan Langman on 2010-09-25 16:36:51.688238
- Added information to the wiki page
- Uploaded the Rhino block diagram and schematics